5bf8fd03e7c4a0da80a4533d589a5e2a80526de6
[openocd.git] / tcl / board / tx25_stk5.cfg
1 # SPDX-License-Identifier: GPL-2.0-or-later
2
3 # -------------------------------------------------------------------------
4 # KaRo TX25 CPU Module on a StarterkitV base board
5 # http://www.karo-electronics.com/tx25.html
6 # -------------------------------------------------------------------------
7
8
9 source [find target/imx25.cfg]
10
11 #-------------------------------------------------------------------------
12 # Declare Nand
13 #-------------------------------------------------------------------------
14
15 nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
16
17
18 $_TARGETNAME configure -event gdb-attach { reset init }
19 $_TARGETNAME configure -event reset-init { tx25_init }
20
21
22 proc tx25_init { } {
23
24 #-------------------------------------------------------------------------
25 # AIPS setup - Only setup MPROTx registers. The PACR default values are good.
26 # Set all MPROTx to be non-bufferable, trusted for R/W,
27 # not forced to user-mode.
28 #-------------------------------------------------------------------------
29
30 mww 0x43f00000 0x77777777
31 mww 0x43f00004 0x77777777
32 mww 0x53f00000 0x77777777
33 mww 0x53f00004 0x77777777
34
35 sleep 100
36
37 #-------------------------------------------------------------------------
38 # MAX (Multi-Layer AHB Crossbar Switch) setup
39 # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
40 #-------------------------------------------------------------------------
41
42 mww 0x43f04000 0x00043210
43 mww 0x43f04100 0x00043210
44 mww 0x43f04200 0x00043210
45 mww 0x43f04300 0x00043210
46 mww 0x43f04400 0x00043210
47
48 # SGPCR - always park on last master
49 mww 0x43f04010 0x10
50 mww 0x43f04110 0x10
51 mww 0x43f04210 0x10
52 mww 0x43f04310 0x10
53 mww 0x43f04410 0x10
54
55 # MGPCR - restore default values
56 mww 0x43f04800 0x0
57 mww 0x43f04900 0x0
58 mww 0x43f04a00 0x0
59 mww 0x43f04b00 0x0
60 mww 0x43f04c00 0x0
61
62 # Configure M3IF registers
63 # M3IF Control Register (M3IFCTL) for MX25
64 # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
65 # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
66 # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
67 # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
68 # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
69 # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
70 # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
71 # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
72 # ----------
73 # 0x00000001
74 mww 0xb8003000 0x00000001
75
76 #-------------------------------------------------------------------------
77 # configure ARM CLK
78 #-------------------------------------------------------------------------
79
80 # Set the Clock CTL (HRM p. 355)
81 mww 0x53F80008 0x20034000
82
83 # Setup Clock Gating CTL 0-2 (HRM p. 357)
84 mww 0x53F8000C 0x1fffffff
85 mww 0x53F80010 0xffffffff
86 mww 0x53F80014 0x000fdfff
87
88 #-------------------------------------------------------------------------
89 # SDRAM initialization
90 #-------------------------------------------------------------------------
91
92 # set to 3.3v SDRAM
93 mww 0x43FAC454 0x00000800
94
95 # reset (set up ESDMISC)
96 mww 0xB8001010 0x00000002
97
98 # Setup for SDRAM Bank 0
99 #-------------------------------------------------------------------------
100
101 # Write ESDCFG0
102 mww 0xB8001004 0x00095728
103
104 # CTL SMode = Precharge command
105 mww 0xB8001000 0x92116480
106 mww 0x80000400 0x00000000
107
108 # CTL SMode = Auto Refresh command
109 mww 0xB8001000 0xA2116480
110 mww 0x80000000 0x0
111 mww 0x80000000 0x0
112 mww 0x80000000 0x0
113 mww 0x80000000 0x0
114 mww 0x80000000 0x0
115 mww 0x80000000 0x0
116 mww 0x80000000 0x0
117 mww 0x80000000 0x0
118
119 # CTL SMode = Load Mode Register command
120 mww 0xB8001000 0xB2116480
121 mwb 0x80000033 0x00
122
123 # CTL SMode = normal
124 mww 0xB8001000 0x82116480
125
126 # Setup for SDRAM Bank 1
127 #-------------------------------------------------------------------------
128
129 # Write ESDCFG1
130 mww 0xB800100C 0x00095728
131
132 # CTL SMode = Precharge command
133 mww 0xB8001008 0x92116480
134 mww 0x90000400 0x00000000
135
136 # CTL SMode = Auto Refresh command
137 mww 0xB8001008 0xA2116480
138 mww 0x90000000 0x00000000
139 mww 0x90000000 0x00000000
140 mww 0x90000000 0x00000000
141 mww 0x90000000 0x00000000
142 mww 0x90000000 0x00000000
143 mww 0x90000000 0x00000000
144 mww 0x90000000 0x00000000
145 mww 0x90000000 0x00000000
146
147 # CTL SMode = Load Mode Register command
148 mww 0xB8001008 0xB2116480
149 mwb 0x90000033 0x00
150
151 # CTL SMode = normal
152 mww 0xB8001008 0x82116480
153
154 # GPIO configuration
155 #-------------------------------------------------------------------------
156
157 mww 0x43FAC02C 0x00000015
158 mww 0x53FD0000 0x01000000
159 mww 0x53FD0004 0x00000080
160 }

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)