tcl/board/vd_swerv_jtag.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 # Cadence virtual debug interface
   3 # RISCV swerv core with Swerv through JTAG
   4
   5 source [find interface/vdebug.cfg]
   6
   7 set _CHIPNAME rv32
   8 set _HARTID 0x00
   9 set _CPUTAPID 0x1000008b
  10 set _MEMSTART 0x00000000
  11 set _MEMSIZE 0x10000
  12
  13 # vdebug select transport
  14 #transport select jtag
  15
  16 # JTAG reset config, frequency and reset delay
  17 reset_config trst_and_srst
  18 adapter speed 50000
  19 adapter srst delay 5
  20
  21 # BFM hierarchical path and input clk period
  22 vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
  23
  24 # DMA Memories to access backdoor (up to 4)
  25 vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE
  26
  27 # need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
  28 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
  29
  30 jtag arp_init-reset
  31
  32 source [find target/vd_riscv.cfg]