tcl/chip/st/spear/spear3xx.tcl

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Generic init scripts for all ST SPEAr3xx family
   4 # http://www.st.com/spear
   5 #
   6 # Date:      2010-09-23
   7 # Author:    Antonio Borneo <borneo.antonio@gmail.com>
   8
   9
  10 # Initialize internal clock
  11 # Default:
  12 # - Crystal =  24 MHz
  13 # - PLL1    = 332 MHz
  14 # - PLL2    = 332 MHz
  15 # - CPU_CLK = 332 MHz
  16 # - DDR_CLK = 332 MHz async
  17 # - HCLK    = 166 MHz
  18 # - PCLK    =  83 MHz
  19 proc sp3xx_clock_default {} {
  20         mww 0xfca00000 0x00000002       ;# set sysclk slow
  21         mww 0xfca00014 0x0ffffff8       ;# set pll timeout to minimum (100us ?!?)
  22
  23         # DDRCORE disable to change frequency
  24         set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
  25         mww 0xfca8002c $val
  26         mww 0xfca8002c $val ;# Yes, write twice!
  27
  28         # programming PLL1
  29         mww 0xfca8000c 0xa600010c       ;# M=166 P=1 N=12
  30         mww 0xfca80008 0x00001c0a       ;# power down
  31         mww 0xfca80008 0x00001c0e       ;# enable
  32         mww 0xfca80008 0x00001c06       ;# strobe
  33         mww 0xfca80008 0x00001c0e
  34         while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
  35
  36         # programming PLL2
  37         mww 0xfca80018 0xa600010c       ;# M=166, P=1, N=12
  38         mww 0xfca80014 0x00001c0a       ;# power down
  39         mww 0xfca80014 0x00001c0e       ;# enable
  40         mww 0xfca80014 0x00001c06       ;# strobe
  41         mww 0xfca80014 0x00001c0e
  42         while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
  43
  44         mww 0xfca80028 0x00000082       ;# enable plltimeen
  45         mww 0xfca80024 0x00000511       ;# set hclkdiv="/2" & pclkdiv="/2"
  46
  47         mww 0xfca00000 0x00000004       ;# setting SYSCTL to NORMAL mode
  48         while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
  49
  50         # Select source of DDR clock
  51         #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
  52         mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
  53
  54         # DDRCORE enable after change frequency
  55         mmw 0xfca8002c 0x20000000 0x00000000
  56 }
  57
  58 proc sp3xx_common_init {} {
  59         mww 0xfca8002c 0xfffffff8       ;# enable clock of all peripherals
  60         mww 0xfca80038 0x00000000       ;# remove reset of all peripherals
  61
  62         mww 0xfca80034 0x0000ffff       ;# enable all RAS clocks
  63         mww 0xfca80040 0x00000000       ;# remove all RAS resets
  64
  65         mww 0xfca800e4 0x78000008       ;# COMP1V8_REG
  66         mww 0xfca800ec 0x78000008       ;# COMP3V3_REG
  67
  68         mww 0xfc000000 0x10000f5f       ;# init SMI and set HW mode
  69         mww 0xfc000000 0x00000f5f
  70
  71         # Initialize Bus Interconnection Matrix
  72         # All ports Round-Robin and lowest priority
  73         mww 0xfca8007c 0x80000007
  74         mww 0xfca80080 0x80000007
  75         mww 0xfca80084 0x80000007
  76         mww 0xfca80088 0x80000007
  77         mww 0xfca8008c 0x80000007
  78         mww 0xfca80090 0x80000007
  79         mww 0xfca80094 0x80000007
  80         mww 0xfca80098 0x80000007
  81         mww 0xfca8009c 0x80000007
  82 }
  83
  84
  85 # Specific init scripts for ST SPEAr300
  86 proc sp300_init {} {
  87         mww 0x99000000 0x00003fff       ;# RAS function enable
  88 }
  89
  90
  91 # Specific init scripts for ST SPEAr310
  92 proc sp310_init {} {
  93         mww 0xb4000008 0x00002ff4       ;# RAS function enable
  94
  95         mww 0xfca80050 0x00000001       ;# Enable clk mem port 1
  96
  97         mww 0xfca8013c 0x2f7bc210       ;# plgpio_pad_drv
  98         mww 0xfca80140 0x017bdef6
  99 }
 100
 101 proc sp310_emi_init {} {
 102         # set EMI pad strength
 103         mmw 0xfca80134 0x0e000000 0x00000000
 104         mmw 0xfca80138 0x0e739ce7 0x00000000
 105         mmw 0xfca8013c 0x00039ce7 0x00000000
 106
 107         # set safe EMI timing as in BootROM
 108         #mww 0x4f000000 0x0000000f      ;# tAP_0_reg
 109         #mww 0x4f000004 0x00000000      ;# tSDP_0_reg
 110         #mww 0x4f000008 0x000000ff      ;# tDPw_0_reg
 111         #mww 0x4f00000c 0x00000111      ;# tDPr_0_reg
 112         #mww 0x4f000010 0x00000002      ;# tDCS_0_reg
 113
 114         # set fast EMI timing as in Linux
 115         mww 0x4f000000 0x00000010       ;# tAP_0_reg
 116         mww 0x4f000004 0x00000005       ;# tSDP_0_reg
 117         mww 0x4f000008 0x0000000a       ;# tDPw_0_reg
 118         mww 0x4f00000c 0x0000000a       ;# tDPr_0_reg
 119         mww 0x4f000010 0x00000005       ;# tDCS_0_re
 120
 121         # 32bit wide, 8/16/32bit access
 122         mww 0x4f000014 0x0000000e       ;# control_0_reg
 123         mww 0x4f000094 0x0000003f       ;# ack_reg
 124 }
 125
 126
 127 # Specific init scripts for ST SPEAr320
 128 proc sp320_init {} {
 129         mww 0xb300000c 0xffffac04       ;# RAS function enable
 130         mww 0xb3000010 0x00000001       ;# RAS mode select
 131 }