tcl/chip/st/stm32/stm32_rcc.tcl

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 set RCC_CR            [expr {$RCC_BASE + 0x00}]
   4 set RCC_CFGR          [expr {$RCC_BASE + 0x04}]
   5 set RCC_CIR           [expr {$RCC_BASE + 0x08}]
   6 set RCC_APB2RSTR      [expr {$RCC_BASE + 0x0c}]
   7 set RCC_APB1RSTR      [expr {$RCC_BASE + 0x10}]
   8 set RCC_AHBENR        [expr {$RCC_BASE + 0x14}]
   9 set RCC_APB2ENR       [expr {$RCC_BASE + 0x18}]
  10 set RCC_APB1ENR       [expr {$RCC_BASE + 0x1c}]
  11 set RCC_BDCR          [expr {$RCC_BASE + 0x20}]
  12 set RCC_CSR           [expr {$RCC_BASE + 0x24}]
  13
  14
  15 proc show_RCC_CR { } {
  16     if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
  17         error $msg
  18     }
  19
  20     show_mmr_bitfield  0  0 $val HSI      { OFF ON }
  21     show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }
  22     show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }
  23     show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }
  24     show_mmr_bitfield 16 16 $val HSEON    { OFF ON }
  25     show_mmr_bitfield 17 17 $val HSERDY   { NOTRDY RDY  }
  26     show_mmr_bitfield 18 18 $val HSEBYP   { NOTBYPASSED BYPASSED }
  27     show_mmr_bitfield 19 19 $val CSSON    { OFF ON }
  28     show_mmr_bitfield 24 24 $val PLLON    { OFF ON }
  29     show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }
  30 }
  31
  32 proc show_RCC_CFGR { } {
  33     if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
  34         error $msg
  35     }
  36
  37
  38     show_mmr_bitfield  1  0 $val  SW     { HSI HSE PLL ILLEGAL }
  39     show_mmr_bitfield  3  2 $val  SWS    { HSI HSE PLL ILLEGAL }
  40     show_mmr_bitfield  7  4 $val  HPRE   { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
  41     show_mmr_bitfield 10  8 $val  PPRE1  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
  42     show_mmr_bitfield 13 11 $val  PPRE2  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
  43     show_mmr_bitfield 15 14 $val  ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
  44     show_mmr_bitfield 16 16 $val  PLLSRC { HSI_div_2 HSE }
  45     show_mmr_bitfield 17 17 $val  PLLXTPRE { hse_div1 hse_div2 }
  46     show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
  47     show_mmr_bitfield 22 22 $val  USBPRE { div1 div1_5 }
  48     show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }
  49 }
  50
  51
  52 proc show_RCC_CIR { } {
  53     if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
  54         error $msg
  55     }
  56
  57 }
  58
  59 proc show_RCC_APB2RSTR { } {
  60     if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
  61         error $msg
  62     }
  63     for { set x 0 } { $x < 32 } { incr x } {
  64         set bits($x) xxx
  65     }
  66     set bits(15) adc3
  67     set bits(14) usart1
  68     set bits(13) tim8
  69     set bits(12) spi1
  70     set bits(11) tim1
  71     set bits(10) adc2
  72     set bits(9) adc1
  73     set bits(8) iopg
  74     set bits(7) iopf
  75     set bits(6) iope
  76     set bits(5) iopd
  77     set bits(4) iopc
  78     set bits(3) iopb
  79     set bits(2) iopa
  80     set bits(1) xxx
  81     set bits(0) afio
  82     show_mmr32_bits bits $val
  83 }
  84
  85 proc show_RCC_APB1RSTR { } {
  86     if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
  87         error $msg
  88     }
  89     set bits(31) xxx
  90     set bits(30) xxx
  91     set bits(29) dac
  92     set bits(28) pwr
  93     set bits(27) bkp
  94     set bits(26) xxx
  95     set bits(25) can
  96     set bits(24) xxx
  97     set bits(23) usb
  98     set bits(22) i2c2
  99     set bits(21) i2c1
 100     set bits(20) uart5
 101     set bits(19) uart4
 102     set bits(18) uart3
 103     set bits(17) uart2
 104     set bits(16) xxx
 105     set bits(15) spi3
 106     set bits(14) spi2
 107     set bits(13) xxx
 108     set bits(12) xxx
 109     set bits(11) wwdg
 110     set bits(10) xxx
 111     set bits(9) xxx
 112     set bits(8) xxx
 113     set bits(7) xxx
 114     set bits(6) xxx
 115     set bits(5) tim7
 116     set bits(4) tim6
 117     set bits(3) tim5
 118     set bits(2) tim4
 119     set bits(1) tim3
 120     set bits(0) tim2
 121     show_mmr32_bits bits $val
 122
 123 }
 124
 125 proc show_RCC_AHBENR   { } {
 126     if [ catch { set val [ show_mmr32_reg RCC_AHBENR  ] } msg ] {
 127         error $msg
 128     }
 129     set bits(31) xxx
 130     set bits(30) xxx
 131     set bits(29) xxx
 132     set bits(28) xxx
 133     set bits(27) xxx
 134     set bits(26) xxx
 135     set bits(25) xxx
 136     set bits(24) xxx
 137     set bits(23) xxx
 138     set bits(22) xxx
 139     set bits(21) xxx
 140     set bits(20) xxx
 141     set bits(19) xxx
 142     set bits(18) xxx
 143     set bits(17) xxx
 144     set bits(16) xxx
 145     set bits(15) xxx
 146     set bits(14) xxx
 147     set bits(13) xxx
 148     set bits(12) xxx
 149     set bits(11) xxx
 150     set bits(10) sdio
 151     set bits(9) xxx
 152     set bits(8) fsmc
 153     set bits(7) xxx
 154     set bits(6) crce
 155     set bits(5) xxx
 156     set bits(4) flitf
 157     set bits(3) xxx
 158     set bits(2) sram
 159     set bits(1) dma2
 160     set bits(0) dma1
 161     show_mmr32_bits bits $val
 162 }
 163
 164 proc show_RCC_APB2ENR  { } {
 165     if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
 166         error $msg
 167     }
 168     set bits(31) xxx
 169     set bits(30) xxx
 170     set bits(29) xxx
 171     set bits(28) xxx
 172     set bits(27) xxx
 173     set bits(26) xxx
 174     set bits(25) xxx
 175     set bits(24) xxx
 176     set bits(23) xxx
 177     set bits(22) xxx
 178     set bits(21) xxx
 179     set bits(20) xxx
 180     set bits(19) xxx
 181     set bits(18) xxx
 182     set bits(17) xxx
 183     set bits(16) xxx
 184     set bits(15) adc3
 185     set bits(14) usart1
 186     set bits(13) tim8
 187     set bits(12) spi1
 188     set bits(11) tim1
 189     set bits(10) adc2
 190     set bits(9) adc1
 191     set bits(8) iopg
 192     set bits(7) iopf
 193     set bits(6) iope
 194     set bits(5) iopd
 195     set bits(4) iopc
 196     set bits(3) iopb
 197     set bits(2) iopa
 198     set bits(1) xxx
 199     set bits(0) afio
 200     show_mmr32_bits bits $val
 201
 202 }
 203
 204 proc show_RCC_APB1ENR  { } {
 205     if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
 206         error $msg
 207     }
 208     set bits(31) xxx
 209     set bits(30) xxx
 210     set bits(29) dac
 211     set bits(28) pwr
 212     set bits(27) bkp
 213     set bits(26) xxx
 214     set bits(25) can
 215     set bits(24) xxx
 216     set bits(23) usb
 217     set bits(22) i2c2
 218     set bits(21) i2c1
 219     set bits(20) usart5
 220     set bits(19) usart4
 221     set bits(18) usart3
 222     set bits(17) usart2
 223     set bits(16) xxx
 224     set bits(15) spi3
 225     set bits(14) spi2
 226     set bits(13) xxx
 227     set bits(12) xxx
 228     set bits(11) wwdg
 229     set bits(10) xxx
 230     set bits(9) xxx
 231     set bits(8) xxx
 232     set bits(7) xxx
 233     set bits(6) xxx
 234     set bits(5) tim7
 235     set bits(4) tim6
 236     set bits(3) tim5
 237     set bits(2) tim4
 238     set bits(1) tim3
 239     set bits(0) tim2
 240     show_mmr32_bits bits $val
 241 }
 242
 243 proc show_RCC_BDCR     { } {
 244     if [ catch { set val [ show_mmr32_reg RCC_BDCR    ] } msg ] {
 245         error $msg
 246     }
 247     for { set x 0 } { $x < 32 } { incr x } {
 248         set bits($x) xxx
 249     }
 250     set bits(0) lseon
 251     set bits(1) lserdy
 252     set bits(2) lsebyp
 253     set bits(8) rtcsel0
 254     set bits(9) rtcsel1
 255     set bits(15) rtcen
 256     set bits(16) bdrst
 257     show_mmr32_bits bits $val
 258 }
 259
 260 proc show_RCC_CSR      { } {
 261     if [ catch { set val [ show_mmr32_reg RCC_CSR     ] } msg ] {
 262         error $msg
 263     }
 264     for { set x 0 } { $x < 32 } { incr x } {
 265         set bits($x) xxx
 266     }
 267     set bits(0) lsion
 268     set bits(1) lsirdy
 269     set bits(24) rmvf
 270     set bits(26) pin
 271     set bits(27) por
 272     set bits(28) sft
 273     set bits(29) iwdg
 274     set bits(30) wwdg
 275     set bits(31) lpwr
 276     show_mmr32_bits bits $val
 277 }
 278
 279 proc show_RCC { } {
 280
 281     show_RCC_CR
 282     show_RCC_CFGR
 283     show_RCC_CIR
 284     show_RCC_APB2RSTR
 285     show_RCC_APB1RSTR
 286     show_RCC_AHBENR
 287     show_RCC_APB2ENR
 288     show_RCC_APB1ENR
 289     show_RCC_BDCR
 290     show_RCC_CSR
 291 }