1 #use combined on interfaces or targets that can't set TRST/SRST separately
2 reset_config srst_only srst_pulls_trst
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
7 set _CHIPNAME at91sam7s
10 if { [info exists ENDIAN] } {
16 if { [info exists CPUTAPID] } {
17 set _CPUTAPID $CPUTAPID
19 set _CPUTAPID 0x3f0f0f0f
22 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
24 set _TARGETNAME $_CHIPNAME.cpu
26 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
27 $_TARGETNAME configure -event reset-init {
29 # RSTC_CR : Reset peripherals
30 mww 0xfffffd00 0xa5000004
32 mww 0xfffffd44 0x00008000
34 mww 0xfffffd08 0xa5000001
35 # CKGR_MOR : enable the main oscillator
36 mww 0xfffffc20 0x00000601
38 # CKGR_PLLR: 96.1097 MHz
39 mww 0xfffffc2c 0x00481c0e
41 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
42 mww 0xfffffc30 0x00000007
44 # MC_FMR: flash mode (FWS=1,FMCN=73)
45 mww 0xffffff60 0x00490100
49 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
51 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
52 set _FLASHNAME $_CHIPNAME.flash
53 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
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