tcl/target/c100regs.tcl

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Note that I basically converted
   4 # u-boot/include/asm-arm/arch/comcerto_100.h
   5 # defines
   6
   7 # this is a work-around for 'global' not working under Linux
   8 # access registers by calling this routine.
   9 # For example:
  10 # set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
  11 proc regs {reg} {
  12     return [dict get [regsC100] $reg ]
  13 }
  14
  15 proc showreg {reg} {
  16     echo [format "0x%x" [dict get [regsC100] $reg ]]
  17 }
  18
  19 proc regsC100 {} {
  20 #/* memcore */
  21 #/* device memory base addresses */
  22 #// device memory sizes
  23 #/* ARAM SIZE=64K */
  24 dict set regsC100 ARAM_SIZE             0x00010000
  25 dict set regsC100 ARAM_BASEADDR 0x0A000000
  26
  27 #/* Hardware Interface Units */
  28 dict set regsC100 APB_BASEADDR  0x10000000
  29 #/* APB_SIZE=16M address range */
  30 dict set regsC100 APB_SIZE              0x01000000
  31
  32 dict set regsC100 EXP_CS0_BASEADDR       0x20000000
  33 dict set regsC100 EXP_CS1_BASEADDR       0x24000000
  34 dict set regsC100 EXP_CS2_BASEADDR       0x28000000
  35 dict set regsC100 EXP_CS3_BASEADDR       0x2C000000
  36 dict set regsC100 EXP_CS4_BASEADDR       0x30000000
  37
  38 dict set regsC100 DDR_BASEADDR           0x80000000
  39
  40 dict set regsC100 TDM_BASEADDR          [expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}]
  41 dict set regsC100 PHI_BASEADDR          [expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}]
  42 dict set regsC100 TDMA_BASEADDR         [expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}]
  43 dict set regsC100 ASA_DDR_BASEADDR              [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}]
  44 dict set regsC100 ASA_ARAM_BASEADDR             [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}]
  45 dict set regsC100 TIMER_BASEADDR                [expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}]
  46 dict set regsC100 ASD_BASEADDR          [expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}]
  47 dict set regsC100 GPIO_BASEADDR         [expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}]
  48 dict set regsC100 UART0_BASEADDR                [expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}]
  49 dict set regsC100 UART1_BASEADDR                [expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}]
  50 dict set regsC100 SPI_BASEADDR          [expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}]
  51 dict set regsC100 I2C_BASEADDR          [expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}]
  52 dict set regsC100 INTC_BASEADDR         [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}]
  53 dict set regsC100 CLKCORE_BASEADDR              [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]
  54 dict set regsC100 PUI_BASEADDR          [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]
  55 dict set regsC100 GEMAC_BASEADDR                [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}]
  56 dict set regsC100 IDMA_BASEADDR         [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}]
  57 dict set regsC100 MEMCORE_BASEADDR              [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}]
  58 dict set regsC100 ASA_EBUS_BASEADDR             [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}]
  59 dict set regsC100 ASA_AAB_BASEADDR              [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}]
  60 dict set regsC100 GEMAC1_BASEADDR               [expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}]
  61 dict set regsC100 EBUS_BASEADDR         [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}]
  62 dict set regsC100 MDMA_BASEADDR         [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}]
  63
  64
  65 #////////////////////////////////////////////////////////////
  66 #//     AHB block                                                                                           //
  67 #////////////////////////////////////////////////////////////
  68 dict set regsC100 ASA_ARAM_PRI_REG      [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}]
  69 dict set regsC100 ASA_ARAM_TC_REG       [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}]
  70 dict set regsC100 ASA_ARAM_TC_CR_REG    [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}]
  71 dict set regsC100 ASA_ARAM_STAT_REG     [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}]
  72
  73 dict set regsC100 ASA_EBUS_PRI_REG      [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}]
  74 dict set regsC100 ASA_EBUS_TC_REG       [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}]
  75 dict set regsC100 ASA_EBUS_TC_CR_REG    [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}]
  76 dict set regsC100 ASA_EBUS_STAT_REG     [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}]
  77
  78 dict set regsC100 IDMA_MASTER           0
  79 dict set regsC100 TDMA_MASTER           1
  80 dict set regsC100 USBIPSEC_MASTER       2
  81 dict set regsC100 ARM0_MASTER           3
  82 dict set regsC100 ARM1_MASTER           4
  83 dict set regsC100 MDMA_MASTER           5
  84
  85 #define IDMA_PRIORITY(level) (level)
  86 #define TDM_PRIORITY(level) (level << 4)
  87 #define USBIPSEC_PRIORITY(level) (level << 8)
  88 #define ARM0_PRIORITY(level) (level << 12)
  89 #define ARM1_PRIORITY(level) (level << 16)
  90 #define MDMA_PRIORITY(level) (level << 20)
  91
  92 dict set regsC100 ASA_TC_REQIDMAEN       [expr {1<<18}]
  93 dict set regsC100 ASA_TC_REQTDMEN        [expr {1<<19}]
  94 dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}]
  95 dict set regsC100 ASA_TC_REQARM0EN       [expr {1<<21}]
  96 dict set regsC100 ASA_TC_REQARM1EN       [expr {1<<22}]
  97 dict set regsC100 ASA_TC_REQMDMAEN       [expr {1<<23}]
  98
  99 dict set regsC100 MEMORY_BASE_ADDR      0x80000000
 100 dict set regsC100 MEMORY_MAX_ADDR       [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}]
 101 dict set regsC100 MEMORY_CR             [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}]
 102 dict set regsC100 ROM_REMAP_EN  0x1
 103
 104 #define HAL_asb_priority(level) \
 105 #*(volatile unsigned *)ASA_PRI_REG = level
 106
 107 #define HAL_aram_priority(level) \
 108 #*(volatile unsigned *)ASA_ARAM_PRI_REG = level
 109
 110 #define HAL_aram_arbitration(arbitration_mask) \
 111 #*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
 112
 113 #define HAL_aram_defmaster(mask) \
 114 #*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
 115
 116 #////////////////////////////////////////////////////////////
 117 #// INTC block                                            //
 118 #////////////////////////////////////////////////////////////
 119
 120 dict set regsC100 INTC_ARM1_CONTROL_REG [expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}]
 121
 122 #////////////////////////////////////////////////////////////
 123 #// TIMER block                                           //
 124 #////////////////////////////////////////////////////////////
 125
 126 dict set regsC100 TIMER0_CNTR_REG       [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}]
 127 dict set regsC100 TIMER0_CURR_COUNT     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}]
 128 dict set regsC100 TIMER1_CNTR_REG       [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}]
 129 dict set regsC100 TIMER1_CURR_COUNT     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}]
 130
 131 dict set regsC100 TIMER2_CNTR_REG       [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}]
 132 dict set regsC100 TIMER2_LBOUND_REG     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}]
 133 dict set regsC100 TIMER2_HBOUND_REG     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}]
 134 dict set regsC100 TIMER2_CURR_COUNT     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}]
 135
 136 dict set regsC100 TIMER3_LOBND  [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}]
 137 dict set regsC100 TIMER3_HIBND  [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}]
 138 dict set regsC100 TIMER3_CTRL           [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}]
 139 dict set regsC100 TIMER3_CURR_COUNT     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}]
 140
 141 dict set regsC100 TIMER_MASK            [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}]
 142 dict set regsC100 TIMER_STATUS  [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]
 143 dict set regsC100 TIMER_ACK             [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]
 144 dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}]
 145 dict set regsC100 TIMER_WDT_CONTROL     [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}]
 146 dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}]
 147
 148
 149
 150 #////////////////////////////////////////////////////////////
 151 #//  EBUS block
 152 #////////////////////////////////////////////////////////////
 153
 154 dict set regsC100 EX_SWRST_REG          [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}]
 155 dict set regsC100 EX_CSEN_REG                   [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}]
 156 dict set regsC100 EX_CS0_SEG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}]
 157 dict set regsC100 EX_CS1_SEG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}]
 158 dict set regsC100 EX_CS2_SEG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}]
 159 dict set regsC100 EX_CS3_SEG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}]
 160 dict set regsC100 EX_CS4_SEG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}]
 161 dict set regsC100 EX_CS0_CFG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}]
 162 dict set regsC100 EX_CS1_CFG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}]
 163 dict set regsC100 EX_CS2_CFG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}]
 164 dict set regsC100 EX_CS3_CFG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}]
 165 dict set regsC100 EX_CS4_CFG_REG                [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}]
 166 dict set regsC100 EX_CS0_TMG1_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}]
 167 dict set regsC100 EX_CS1_TMG1_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}]
 168 dict set regsC100 EX_CS2_TMG1_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}]
 169 dict set regsC100 EX_CS3_TMG1_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}]
 170 dict set regsC100 EX_CS4_TMG1_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}]
 171 dict set regsC100 EX_CS0_TMG2_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}]
 172 dict set regsC100 EX_CS1_TMG2_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}]
 173 dict set regsC100 EX_CS2_TMG2_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}]
 174 dict set regsC100 EX_CS3_TMG2_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}]
 175 dict set regsC100 EX_CS4_TMG2_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}]
 176 dict set regsC100 EX_CS0_TMG3_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}]
 177 dict set regsC100 EX_CS1_TMG3_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}]
 178 dict set regsC100 EX_CS2_TMG3_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}]
 179 dict set regsC100 EX_CS3_TMG3_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}]
 180 dict set regsC100 EX_CS4_TMG3_REG               [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}]
 181 dict set regsC100 EX_CLOCK_DIV_REG              [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}]
 182
 183 dict set regsC100 EX_MFSM_REG           [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]
 184 dict set regsC100 EX_MFSM_REG           [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]
 185 dict set regsC100 EX_CSFSM_REG          [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}]
 186 dict set regsC100 EX_WRFSM_REG          [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}]
 187 dict set regsC100 EX_RDFSM_REG          [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}]
 188
 189
 190 dict set regsC100 EX_CLK_EN             0x00000001
 191 dict set regsC100 EX_CSBOOT_EN  0x00000002
 192 dict set regsC100 EX_CS0_EN             0x00000002
 193 dict set regsC100 EX_CS1_EN             0x00000004
 194 dict set regsC100 EX_CS2_EN             0x00000008
 195 dict set regsC100 EX_CS3_EN             0x00000010
 196 dict set regsC100 EX_CS4_EN             0x00000020
 197
 198 dict set regsC100 EX_MEM_BUS_8  0x00000000
 199 dict set regsC100 EX_MEM_BUS_16       0x00000002
 200 dict set regsC100 EX_MEM_BUS_32 0x00000004
 201 dict set regsC100 EX_CS_HIGH            0x00000008
 202 dict set regsC100 EX_WE_HIGH            0x00000010
 203 dict set regsC100 EX_RE_HIGH            0x00000020
 204 dict set regsC100 EX_ALE_MODE           0x00000040
 205 dict set regsC100 EX_STRB_MODE  0x00000080
 206 dict set regsC100 EX_DM_MODE            0x00000100
 207 dict set regsC100 EX_NAND_MODE  0x00000200
 208 dict set regsC100 EX_RDY_EN             0x00000400
 209 dict set regsC100 EX_RDY_EDGE           0x00000800
 210
 211 #////////////////////////////////////////////////////////////
 212 #//  GPIO block
 213 #////////////////////////////////////////////////////////////
 214
 215 # GPIO outputs register
 216 dict set regsC100 GPIO_OUTPUT_REG               [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}]
 217 # GPIO Output Enable register
 218 dict set regsC100 GPIO_OE_REG                   [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}]
 219 dict set regsC100 GPIO_HI_INT_ENABLE_REG        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}]
 220 dict set regsC100 GPIO_LO_INT_ENABLE_REG        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}]
 221 # GPIO input register
 222 dict set regsC100 GPIO_INPUT_REG                [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}]
 223 dict set regsC100 APB_ACCESS_WS_REG             [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}]
 224 dict set regsC100 MUX_CONF_REG          [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}]
 225 dict set regsC100 SYSCONF_REG                   [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}]
 226 dict set regsC100 GPIO_ARM_ID_REG               [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}]
 227 dict set regsC100 GPIO_BOOTSTRAP_REG            [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}]
 228 dict set regsC100 GPIO_LOCK_REG         [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}]
 229 dict set regsC100 GPIO_IOCTRL_REG               [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}]
 230 dict set regsC100 GPIO_DEVID_REG                [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}]
 231
 232 dict set regsC100 GPIO_IOCTRL_A15A16    0x00000001
 233 dict set regsC100 GPIO_IOCTRL_A17A18    0x00000002
 234 dict set regsC100 GPIO_IOCTRL_A19A21    0x00000004
 235 dict set regsC100 GPIO_IOCTRL_TMREVT0   0x00000008
 236 dict set regsC100 GPIO_IOCTRL_TMREVT1   0x00000010
 237 dict set regsC100 GPIO_IOCTRL_GPBT3     0x00000020
 238 dict set regsC100 GPIO_IOCTRL_I2C       0x00000040
 239 dict set regsC100 GPIO_IOCTRL_UART0     0x00000080
 240 dict set regsC100 GPIO_IOCTRL_UART1     0x00000100
 241 dict set regsC100 GPIO_IOCTRL_SPI       0x00000200
 242 dict set regsC100 GPIO_IOCTRL_HBMODE    0x00000400
 243
 244 dict set regsC100 GPIO_IOCTRL_VAL       0x55555555
 245
 246 dict set regsC100 GPIO_0                        0x01
 247 dict set regsC100 GPIO_1                        0x02
 248 dict set regsC100 GPIO_2                        0x04
 249 dict set regsC100 GPIO_3                        0x08
 250 dict set regsC100 GPIO_4                        0x10
 251 dict set regsC100 GPIO_5                        0x20
 252 dict set regsC100 GPIO_6                        0x40
 253 dict set regsC100 GPIO_7                        0x80
 254
 255 dict set regsC100 GPIO_RISING_EDGE      1
 256 dict set regsC100 GPIO_FALLING_EDGE     2
 257 dict set regsC100 GPIO_BOTH_EDGES       3
 258
 259 #////////////////////////////////////////////////////////////
 260 #// UART
 261 #////////////////////////////////////////////////////////////
 262
 263 dict set regsC100 UART0_RBR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
 264 dict set regsC100 UART0_THR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
 265 dict set regsC100 UART0_DLL             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]
 266 dict set regsC100 UART0_IER             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]
 267 dict set regsC100 UART0_DLH             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]
 268 dict set regsC100 UART0_IIR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]
 269 dict set regsC100 UART0_FCR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]
 270 dict set regsC100 UART0_LCR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}]
 271 dict set regsC100 UART0_MCR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}]
 272 dict set regsC100 UART0_LSR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}]
 273 dict set regsC100 UART0_MSR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}]
 274 dict set regsC100 UART0_SCR             [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}]
 275
 276 dict set regsC100 UART1_RBR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
 277 dict set regsC100 UART1_THR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
 278 dict set regsC100 UART1_DLL             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]
 279 dict set regsC100 UART1_IER             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]
 280 dict set regsC100 UART1_DLH             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]
 281 dict set regsC100 UART1_IIR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]
 282 dict set regsC100 UART1_FCR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]
 283 dict set regsC100 UART1_LCR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}]
 284 dict set regsC100 UART1_MCR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}]
 285 dict set regsC100 UART1_LSR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}]
 286 dict set regsC100 UART1_MSR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}]
 287 dict set regsC100 UART1_SCR             [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}]
 288
 289 # /* default */
 290 dict set regsC100 LCR_CHAR_LEN_5                0x00
 291 dict set regsC100 LCR_CHAR_LEN_6                0x01
 292 dict set regsC100 LCR_CHAR_LEN_7                0x02
 293 dict set regsC100 LCR_CHAR_LEN_8                0x03
 294 #/* One stop bit! - default */
 295 dict set regsC100 LCR_ONE_STOP          0x00
 296 #/* Two stop bit! */
 297 dict set regsC100 LCR_TWO_STOP          0x04
 298 #/* Parity Enable */
 299 dict set regsC100 LCR_PEN                       0x08
 300 dict set regsC100 LCR_PARITY_NONE               0x00
 301 #/* Even Parity Select */
 302 dict set regsC100 LCR_EPS                       0x10
 303 #/* Enable Parity  Stuff */
 304 dict set regsC100 LCR_PS                        0x20
 305 #/* Start Break */
 306 dict set regsC100 LCR_SBRK                      0x40
 307 #/* Parity Stuff Bit */
 308 dict set regsC100 LCR_PSB                       0x80
 309 #/* UART 16550 Divisor Latch Assess */
 310 dict set regsC100 LCR_DLAB                      0x80
 311
 312 #/* FIFO Error Status */
 313 dict set regsC100 LSR_FIFOE             [expr {1 << 7}]
 314 #/* Transmitter Empty */
 315 dict set regsC100 LSR_TEMT              [expr {1 << 6}]
 316 #/* Transmit Data Request */
 317 dict set regsC100 LSR_TDRQ              [expr {1 << 5}]
 318 #/* Break Interrupt */
 319 dict set regsC100 LSR_BI                        [expr {1 << 4}]
 320 #/* Framing Error */
 321 dict set regsC100 LSR_FE                        [expr {1 << 3}]
 322 #/* Parity Error */
 323 dict set regsC100 LSR_PE                        [expr {1 << 2}]
 324 #/* Overrun Error */
 325 dict set regsC100 LSR_OE                        [expr {1 << 1}]
 326 #/* Data Ready */
 327 dict set regsC100 LSR_DR                        [expr {1 << 0}]
 328
 329 #/* DMA Requests Enable */
 330 dict set regsC100 IER_DMAE                      [expr {1 << 7}]
 331 #/* UART Unit Enable */
 332 dict set regsC100 IER_UUE                       [expr {1 << 6}]
 333 #/* NRZ coding Enable */
 334 dict set regsC100 IER_NRZE                      [expr {1 << 5}]
 335 #/* Receiver Time Out Interrupt Enable */
 336 dict set regsC100 IER_RTIOE                     [expr {1 << 4}]
 337 #/* Modem Interrupt Enable */
 338 dict set regsC100 IER_MIE                       [expr {1 << 3}]
 339 #/* Receiver Line Status Interrupt Enable */
 340 dict set regsC100 IER_RLSE                      [expr {1 << 2}]
 341 #/* Transmit Data request Interrupt Enable */
 342 dict set regsC100 IER_TIE                       [expr {1 << 1}]
 343 #/* Receiver Data Available Interrupt Enable */
 344 dict set regsC100 IER_RAVIE                     [expr {1 << 0}]
 345
 346 #/* FIFO Mode Enable Status */
 347 dict set regsC100 IIR_FIFOES1                   [expr {1 << 7}]
 348 #/* FIFO Mode Enable Status */
 349 dict set regsC100 IIR_FIFOES0                   [expr {1 << 6}]
 350 #/* Time Out Detected */
 351 dict set regsC100 IIR_TOD                       [expr {1 << 3}]
 352 #/* Interrupt Source Encoded */
 353 dict set regsC100 IIR_IID2                      [expr {1 << 2}]
 354 #/* Interrupt Source Encoded */
 355 dict set regsC100 IIR_IID1                      [expr {1 << 1}]
 356 #/* Interrupt Pending (active low) */
 357 dict set regsC100 IIR_IP                        [expr {1 << 0}]
 358
 359 #/* UART 16550 FIFO Control Register */
 360 dict set regsC100 FCR_FIFOEN            0x01
 361 dict set regsC100 FCR_RCVRRES           0x02
 362 dict set regsC100 FCR_XMITRES           0x04
 363
 364 #/* Interrupt Enable Register */
 365 #// UART 16550
 366 #// Enable Received Data Available Interrupt
 367 dict set regsC100 IER_RXTH              0x01
 368 #// Enable Transmitter Empty Interrupt
 369 dict set regsC100 IER_TXTH              0x02
 370
 371
 372
 373 #////////////////////////////////////////////////////////////
 374 #// CLK  + RESET block
 375 #////////////////////////////////////////////////////////////
 376
 377 dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}]
 378 dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}]
 379 dict set regsC100 CLKCORE_PLL_STATUS            [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}]
 380 dict set regsC100 CLKCORE_CLKDIV_CNTRL  [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}]
 381 dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}]
 382 dict set regsC100 CLKCORE_FSYNC_CNTRL           [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}]
 383 dict set regsC100 CLKCORE_CLK_PWR_DWN           [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}]
 384 dict set regsC100 CLKCORE_RNG_CNTRL             [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}]
 385 dict set regsC100 CLKCORE_RNG_STATUS            [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}]
 386 dict set regsC100 CLKCORE_ARM_CLK_CNTRL2        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}]
 387 dict set regsC100 CLKCORE_TDM_REF_DIV_RST       [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}]
 388
 389 dict set regsC100 ARM_PLL_BY_CTRL       0x80000000
 390 dict set regsC100 ARM_AHB_BYP           0x04000000
 391 dict set regsC100 PLL_DISABLE           0x02000000
 392 dict set regsC100 PLL_CLK_BYPASS        0x01000000
 393
 394 dict set regsC100 AHB_PLL_BY_CTRL       0x80000000
 395 dict set regsC100 DIV_BYPASS            0x40000000
 396 dict set regsC100 SYNC_MODE             0x20000000
 397
 398 dict set regsC100 EPHY_CLKDIV_BYPASS    0x00200000
 399 dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT       16
 400 dict set regsC100 PUI_CLKDIV_BYPASS     0x00004000
 401 dict set regsC100 PUI_CLKDIV_SRCCLK     0x00002000
 402 dict set regsC100 PUI_CLKDIV_RATIO_SHIFT        8
 403 dict set regsC100 PCI_CLKDIV_BYPASS     0x00000020
 404 dict set regsC100 PCI_CLKDIV_RATIO_SHIFT        0
 405
 406 dict set regsC100 ARM0_CLK_PD           0x00200000
 407 dict set regsC100 ARM1_CLK_PD           0x00100000
 408 dict set regsC100 EPHY_CLK_PD           0x00080000
 409 dict set regsC100 TDM_CLK_PD            0x00040000
 410 dict set regsC100 PUI_CLK_PD            0x00020000
 411 dict set regsC100 PCI_CLK_PD            0x00010000
 412 dict set regsC100 MDMA_AHBCLK_PD        0x00000400
 413 dict set regsC100 I2CSPI_AHBCLK_PD      0x00000200
 414 dict set regsC100 UART_AHBCLK_PD        0x00000100
 415 dict set regsC100 IPSEC_AHBCLK_PD       0x00000080
 416 dict set regsC100 TDM_AHBCLK_PD 0x00000040
 417 dict set regsC100 USB1_AHBCLK_PD        0x00000020
 418 dict set regsC100 USB0_AHBCLK_PD        0x00000010
 419 dict set regsC100 GEMAC1_AHBCLK_PD      0x00000008
 420 dict set regsC100 GEMAC0_AHBCLK_PD      0x00000004
 421 dict set regsC100 PUI_AHBCLK_PD 0x00000002
 422 dict set regsC100 HIF_AHBCLK_PD 0x00000001
 423
 424 dict set regsC100 ARM1_DIV_BP           0x00001000
 425 dict set regsC100 ARM1_DIV_VAL_SHIFT    8
 426 dict set regsC100 ARM0_DIV_BP           0x00000010
 427 dict set regsC100 ARM0_DIV_VAL_SHIFT    0
 428
 429 dict set regsC100 AHBCLK_PLL_LOCK       0x00000002
 430 dict set regsC100 FCLK_PLL_LOCK 0x00000001
 431
 432
 433 #// reset block
 434 dict set regsC100 BLOCK_RESET_REG               [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}]
 435 dict set regsC100 CSP_RESET_REG         [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}]
 436
 437 dict set regsC100 RNG_RST               0x1000
 438 dict set regsC100 IPSEC_RST             0x0800
 439 dict set regsC100 DDR_RST               0x0400
 440 dict set regsC100 USB1_PHY_RST  0x0200
 441 dict set regsC100 USB0_PHY_RST  0x0100
 442 dict set regsC100 USB1_RST              0x0080
 443 dict set regsC100 USB0_RST              0x0040
 444 dict set regsC100 GEMAC1_RST            0x0020
 445 dict set regsC100 GEMAC0_RST            0x0010
 446 dict set regsC100 TDM_RST               0x0008
 447 dict set regsC100 PUI_RST               0x0004
 448 dict set regsC100 HIF_RST               0x0002
 449 dict set regsC100 PCI_RST               0x0001
 450
 451 #////////////////////////////////////////////////////////////////
 452 #//     DDR  CONTROLLER block
 453 #////////////////////////////////////////////////////////////////
 454
 455 dict set regsC100 DDR_CONFIG_BASEADDR   0x0D000000
 456 dict set regsC100 DENALI_CTL_00_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}]
 457 dict set regsC100 DENALI_CTL_01_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}]
 458 dict set regsC100 DENALI_CTL_02_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}]
 459 dict set regsC100 DENALI_CTL_03_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}]
 460 dict set regsC100 DENALI_CTL_04_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}]
 461 dict set regsC100 DENALI_CTL_05_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}]
 462 dict set regsC100 DENALI_CTL_06_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}]
 463 dict set regsC100 DENALI_CTL_07_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}]
 464 dict set regsC100 DENALI_CTL_08_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}]
 465 dict set regsC100 DENALI_CTL_09_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}]
 466 dict set regsC100 DENALI_CTL_10_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}]
 467 dict set regsC100 DENALI_CTL_11_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}]
 468 dict set regsC100 DENALI_CTL_12_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}]
 469 dict set regsC100 DENALI_CTL_13_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}]
 470 dict set regsC100 DENALI_CTL_14_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}]
 471 dict set regsC100 DENALI_CTL_15_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}]
 472 dict set regsC100 DENALI_CTL_16_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}]
 473 dict set regsC100 DENALI_CTL_17_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}]
 474 dict set regsC100 DENALI_CTL_18_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}]
 475 dict set regsC100 DENALI_CTL_19_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}]
 476 dict set regsC100 DENALI_CTL_20_DATA    [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}]
 477
 478 # 32-bit value
 479 dict set regsC100 DENALI_READY_CHECK         [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}]
 480 # 8-bit
 481 dict set regsC100 DENALI_WR_DQS              [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}]
 482 # 8-bit
 483 dict set regsC100 DENALI_DQS_OUT             [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}]
 484 # 8-bit
 485 dict set regsC100 DENALI_DQS_DELAY0          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}]
 486 # 8-bit
 487 dict set regsC100 DENALI_DQS_DELAY1          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}]
 488 # 8-bit
 489 dict set regsC100 DENALI_DQS_DELAY2          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}]
 490 # 8-bit
 491 dict set regsC100 DENALI_DQS_DELAY3          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}]
 492
 493
 494 # end of proc regsC100
 495 }