tcl/target/davinci.cfg

   1 #
   2 # Utility code for DaVinci-family chips
   3 #
   4
   5 # davinci_pinmux:  assigns PINMUX$reg <== $value
   6 proc davinci_pinmux {soc reg value} {
   7         mww [expr [dict get $soc sysbase] + 4 * $reg] $value
   8 }
   9
  10 # mrw: "memory read word", returns value of $reg
  11 proc mrw {reg} {
  12         set value ""
  13         ocd_mem2array value 32 $reg 1
  14         return $value(0)
  15 }
  16
  17 # mmw: "memory modify word", updates value of $reg
  18 #       $reg <== ((value & ~$clearbits) | $setbits)
  19 proc mmw {reg setbits clearbits} {
  20         set old [mrw $reg]
  21         set new [expr ($old & ~$clearbits) | $setbits]
  22         mww $reg $new
  23 }
  24
  25 #
  26 # pll_setup: initialize PLL
  27 #  - pll_addr ... physical addr of controller
  28 #  - mult ... pll multiplier
  29 #  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
  30 #
  31 # For PLLs that don't have a given register (e.g. plldiv8), or where a
  32 # given divider is non-programmable, caller provides *NO* config mapping.
  33 #
  34
  35 # PLL version 0x02: tested on dm355
  36 # REVISIT:  On dm6446 and dm357 the PLLRST polarity is different.
  37 proc pll_v02_setup {pll_addr mult config} {
  38         set pll_ctrl_addr [expr $pll_addr + 0x100]
  39         set pll_ctrl [mrw $pll_ctrl_addr]
  40
  41         # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
  42         # NOTE:  this assumes we should clear that bit
  43         set pll_ctrl [expr $pll_ctrl & ~0x0100]
  44         mww $pll_ctrl_addr $pll_ctrl
  45
  46         # 2 - clear PLLENSRC (bit 5)
  47         set pll_ctrl [expr $pll_ctrl & ~0x0020]
  48         mww $pll_ctrl_addr $pll_ctrl
  49
  50         # 3 - clear PLLEN (bit 0) ... enter bypass mode
  51         set pll_ctrl [expr $pll_ctrl & ~0x0001]
  52         mww $pll_ctrl_addr $pll_ctrl
  53
  54         # 4 - wait at least 4 refclk cycles
  55         sleep 1
  56
  57         # 5 - set PLLRST (bit 3)
  58         set pll_ctrl [expr $pll_ctrl | 0x0008]
  59         mww $pll_ctrl_addr $pll_ctrl
  60
  61         # 6 - set PLLDIS (bit 4)
  62         set pll_ctrl [expr $pll_ctrl | 0x0010]
  63         mww $pll_ctrl_addr $pll_ctrl
  64
  65         # 7 - clear PLLPWRDN (bit 1)
  66         set pll_ctrl [expr $pll_ctrl & ~0x0002]
  67         mww $pll_ctrl_addr $pll_ctrl
  68
  69         # 8 - clear PLLDIS (bit 4)
  70         set pll_ctrl [expr $pll_ctrl & ~0x0010]
  71         mww $pll_ctrl_addr $pll_ctrl
  72
  73         # 9 - optional:  write prediv, postdiv, and pllm
  74         # NOTE:  for dm355 PLL1, postdiv is controlled via MISC register
  75         mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
  76         if { [dict exists $config prediv] } {
  77                 set div [dict get $config prediv]
  78                 set div [expr 0x8000 | ($div - 1)]
  79                 mww [expr $pll_addr + 0x0114] $div
  80         }
  81         if { [dict exists $config postdiv] } {
  82                 set div [dict get $config postdiv]
  83                 set div [expr 0x8000 | ($div - 1)]
  84                 mww [expr $pll_addr + 0x0128] $div
  85         }
  86
  87         # 10 - optional:  set plldiv1, plldiv2, ...
  88         # NOTE:  this assumes some registers have their just-reset values:
  89         #       - PLLSTAT.GOSTAT is clear when we enter
  90         #       - ALNCTL has everything set
  91         set go 0
  92         if { [dict exists $config div1] } {
  93                 set div [dict get $config div1]
  94                 set div [expr 0x8000 | ($div - 1)]
  95                 mww [expr $pll_addr + 0x0118] $div
  96                 set go 1
  97         }
  98         if { [dict exists $config div2] } {
  99                 set div [dict get $config div2]
 100                 set div [expr 0x8000 | ($div - 1)]
 101                 mww [expr $pll_addr + 0x011c] $div
 102                 set go 1
 103         }
 104         if { [dict exists $config div3] } {
 105                 set div [dict get $config div3]
 106                 set div [expr 0x8000 | ($div - 1)]
 107                 mww [expr $pll_addr + 0x0120] $div
 108                 set go 1
 109         }
 110         if { [dict exists $config div4] } {
 111                 set div [dict get $config div4]
 112                 set div [expr 0x8000 | ($div - 1)]
 113                 mww [expr $pll_addr + 0x0160] $div
 114                 set go 1
 115         }
 116         if { [dict exists $config div5] } {
 117                 set div [dict get $config div5]
 118                 set div [expr 0x8000 | ($div - 1)]
 119                 mww [expr $pll_addr + 0x0164] $div
 120                 set go 1
 121         }
 122         if {$go != 0} {
 123                 # write pllcmd.GO; poll pllstat.GO
 124                 mww [expr $pll_addr + 0x0138] 0x01
 125                 set pllstat [expr $pll_addr + 0x013c]
 126                 while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
 127         }
 128
 129         # 11 - wait at least 5 usec for reset to finish
 130         # (assume covered by overheads including JTAG messaging)
 131
 132         # 12 - clear PLLRST (bit 3)
 133         set pll_ctrl [expr $pll_ctrl & ~0x0008]
 134         mww $pll_ctrl_addr $pll_ctrl
 135
 136         # 13 - wait at least 8000 refclk cycles for PLL to lock
 137         # if we assume 24 MHz (slowest osc), that's 1/3 msec
 138         sleep 3
 139
 140         # 14 - set PLLEN (bit 0) ... leave bypass mode
 141         set pll_ctrl [expr $pll_ctrl | 0x0001]
 142         mww $pll_ctrl_addr $pll_ctrl
 143 }
 144
 145 # NOTE:  dm6446 requires EMURSTIE set in MDCTL before certain
 146 # modules can be enabled.
 147
 148 # prepare a non-DSP module to be enabled; finish with psc_go
 149 proc psc_enable {module} {
 150         set psc_addr 0x01c41000
 151         # write MDCTL
 152         mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
 153 }
 154
 155 # execute non-DSP PSC transition(s) set up by psc_enable
 156 proc psc_go {} {
 157         set psc_addr 0x01c41000
 158         set ptstat_addr [expr $psc_addr + 0x0128]
 159
 160         # just in case PTSTAT.go isn't clear
 161         while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
 162
 163         # write PTCMD.go ... ignoring any DSP power domain
 164         mww [expr $psc_addr + 0x0120] 1
 165
 166         # wait for PTSTAT.go to clear (again ignoring DSP power domain)
 167         while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
 168 }