tcl/target/esp32.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 #
   3 # The ESP32 only supports JTAG.
   4 transport select jtag
   5
   6 # Source the ESP common configuration file
   7 source [find target/esp_common.cfg]
   8
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME esp32
  13 }
  14
  15 if { [info exists CPUTAPID] } {
  16         set _CPUTAPID $CPUTAPID
  17 } else {
  18         set _CPUTAPID 0x120034e5
  19 }
  20
  21 if { [info exists ESP32_ONLYCPU] } {
  22         set _ONLYCPU $ESP32_ONLYCPU
  23 } else {
  24         set _ONLYCPU 2
  25 }
  26
  27 if { [info exists ESP32_FLASH_VOLTAGE] } {
  28         set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
  29 } else {
  30         set _FLASH_VOLTAGE 3.3
  31 }
  32
  33 set _CPU0NAME cpu0
  34 set _CPU1NAME cpu1
  35 set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
  36 set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
  37
  38 jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
  39 if { $_ONLYCPU != 1 } {
  40         jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
  41 } else {
  42         jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
  43 }
  44
  45 # PRO-CPU
  46 target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
  47 # APP-CPU
  48 if { $_ONLYCPU != 1 } {
  49         target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
  50         target smp $_TARGETNAME_0 $_TARGETNAME_1
  51 }
  52
  53 $_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE
  54 $_TARGETNAME_0 xtensa maskisr on
  55 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
  56 $_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
  57
  58 $_TARGETNAME_0 configure -event gdb-attach {
  59         $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
  60         # necessary to auto-probe flash bank when GDB is connected
  61         halt 1000
  62 }
  63
  64 if { $_ONLYCPU != 1 } {
  65         $_TARGETNAME_1 configure -event gdb-attach {
  66                 $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
  67                 # necessary to auto-probe flash bank when GDB is connected
  68                 halt 1000
  69         }
  70         $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
  71 }
  72
  73 $_TARGETNAME_0 configure -event examine-end {
  74     # Need to enable to set 'semihosting_basedir'
  75     arm semihosting enable
  76     arm semihosting_resexit enable
  77     if { [info exists _SEMIHOST_BASEDIR] } {
  78         if { $_SEMIHOST_BASEDIR != "" } {
  79             arm semihosting_basedir $_SEMIHOST_BASEDIR
  80         }
  81     }
  82 }
  83
  84 if { $_ONLYCPU != 1 } {
  85         $_TARGETNAME_1 configure -event examine-end {
  86                 # Need to enable to set 'semihosting_basedir'
  87                 arm semihosting enable
  88                 arm semihosting_resexit enable
  89                 if { [info exists _SEMIHOST_BASEDIR] } {
  90                         if { $_SEMIHOST_BASEDIR != "" } {
  91                                 arm semihosting_basedir $_SEMIHOST_BASEDIR
  92                         }
  93                 }
  94         }
  95 }
  96
  97 gdb_breakpoint_override hard
  98
  99 source [find target/xtensa-core-esp32.cfg]