tcl/target/esp32s3.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 #
   3
   4 # Source the ESP common configuration file.
   5 source [find target/esp_common.cfg]
   6
   7 # Target specific global variables
   8 set _CHIPNAME                                   "esp32s3"
   9 set _CPUTAPID                                   0x120034e5
  10 set _ESP_ARCH                                   "xtensa"
  11 set _ONLYCPU                                    3
  12 set _ESP_SMP_TARGET                             1
  13 set _ESP_SMP_BREAK                              1
  14 set _ESP_EFUSE_MAC_ADDR_REG     0x60007044
  15
  16 if { [info exists ESP32_S3_ONLYCPU] } {
  17         set _ONLYCPU $ESP32_S3_ONLYCPU
  18 }
  19
  20 proc esp32s3_memprot_is_enabled { } {
  21         # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
  22         if { [get_mmr_bit 0x600C10C0 0] != 0 } {
  23                 return 1
  24         }
  25         # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
  26         if { [get_mmr_bit 0x600C1124 0] != 0 } {
  27                 return 1
  28         }
  29         # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
  30         if { [get_mmr_bit 0x600C11D0 0] != 0 } {
  31                 return 1
  32         }
  33         # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
  34         if { [get_mmr_bit 0x600C10D8 0] != 0 } {
  35                 return 1
  36         }
  37         # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
  38         if { [get_mmr_bit 0x600C10FC 0] != 0 } {
  39                 return 1
  40         }
  41         # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
  42         if { [get_mmr_bit 0x600C10E4 0] != 0 } {
  43                 return 1
  44         }
  45         # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
  46         if { [get_mmr_bit 0x600C10F0 0] != 0 } {
  47                 return 1
  48         }
  49         # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
  50         if { [get_mmr_bit 0x600C1104 0] != 0 } {
  51                 return 1
  52         }
  53         # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
  54         if { [get_mmr_bit 0x600C1114 0] != 0 } {
  55                 return 1
  56         }
  57         # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
  58         if { [get_mmr_bit 0x600C119C 0] != 0 } {
  59                 return 1
  60         }
  61         # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
  62         if { [get_mmr_bit 0x600C1248 0] != 0 } {
  63                 return 1
  64         }
  65         return 0
  66 }
  67
  68 proc esp32s3_soc_reset { } {
  69         soft_reset_halt
  70 }
  71
  72 create_esp_target $_ESP_ARCH
  73
  74 source [find target/xtensa-core-esp32s3.cfg]