tcl/target/esp32s3.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 #
   3 # The ESP32-S3 only supports JTAG.
   4 transport select jtag
   5
   6 set CPU_MAX_ADDRESS 0xFFFFFFFF
   7 source [find bitsbytes.tcl]
   8 source [find memory.tcl]
   9 source [find mmr_helpers.tcl]
  10 # Source the ESP common configuration file
  11 source [find target/esp_common.cfg]
  12
  13
  14 if { [info exists CHIPNAME] } {
  15         set _CHIPNAME $CHIPNAME
  16 } else {
  17         set _CHIPNAME esp32s3
  18 }
  19
  20 if { [info exists CPUTAPID] } {
  21         set _CPUTAPID $CPUTAPID
  22 } else {
  23         set _CPUTAPID 0x120034e5
  24 }
  25
  26 if { [info exists ESP32_S3_ONLYCPU] } {
  27         set _ONLYCPU $ESP32_S3_ONLYCPU
  28 } else {
  29         set _ONLYCPU 2
  30 }
  31
  32 set _CPU0NAME cpu0
  33 set _CPU1NAME cpu1
  34 set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
  35 set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
  36
  37 jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
  38 if { $_ONLYCPU != 1 } {
  39         jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
  40 } else {
  41         jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
  42 }
  43
  44 proc esp32s3_memprot_is_enabled { } {
  45         # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
  46         if { [get_mmr_bit 0x600C10C0 0] != 0 } {
  47                 return 1
  48         }
  49         # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
  50         if { [get_mmr_bit 0x600C1124 0] != 0 } {
  51                 return 1
  52         }
  53         # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
  54         if { [get_mmr_bit 0x600C11D0 0] != 0 } {
  55                 return 1
  56         }
  57         # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
  58         if { [get_mmr_bit 0x600C10D8 0] != 0 } {
  59                 return 1
  60         }
  61         # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
  62         if { [get_mmr_bit 0x600C10FC 0] != 0 } {
  63                 return 1
  64         }
  65         # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
  66         if { [get_mmr_bit 0x600C10E4 0] != 0 } {
  67                 return 1
  68         }
  69         # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
  70         if { [get_mmr_bit 0x600C10F0 0] != 0 } {
  71                 return 1
  72         }
  73         # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
  74         if { [get_mmr_bit 0x600C1104 0] != 0 } {
  75                 return 1
  76         }
  77         # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
  78         if { [get_mmr_bit 0x600C1114 0] != 0 } {
  79                 return 1
  80         }
  81         # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
  82         if { [get_mmr_bit 0x600C119C 0] != 0 } {
  83                 return 1
  84         }
  85         # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
  86         if { [get_mmr_bit 0x600C1248 0] != 0 } {
  87                 return 1
  88         }
  89         return 0
  90 }
  91
  92 # PRO-CPU
  93 target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
  94 # APP-CPU
  95 if { $_ONLYCPU != 1 } {
  96         target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
  97         target smp $_TARGETNAME_0 $_TARGETNAME_1
  98 }
  99
 100 $_TARGETNAME_0 xtensa maskisr on
 101 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
 102 $_TARGETNAME_0 configure -event examine-end {
 103         # Need to enable to set 'semihosting_basedir'
 104         arm semihosting enable
 105         arm semihosting_resexit enable
 106         if { [info exists _SEMIHOST_BASEDIR] } {
 107                 if { $_SEMIHOST_BASEDIR != "" } {
 108                         arm semihosting_basedir $_SEMIHOST_BASEDIR
 109                 }
 110         }
 111 }
 112
 113 if { $_ONLYCPU != 1 } {
 114         $_TARGETNAME_1 configure -event examine-end {
 115                 # Need to enable to set 'semihosting_basedir'
 116                 arm semihosting enable
 117                 arm semihosting_resexit enable
 118                 if { [info exists _SEMIHOST_BASEDIR] } {
 119                         if { $_SEMIHOST_BASEDIR != "" } {
 120                                 arm semihosting_basedir $_SEMIHOST_BASEDIR
 121                         }
 122                 }
 123         }
 124 }
 125
 126 $_TARGETNAME_0 configure -event gdb-attach {
 127         $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
 128         # necessary to auto-probe flash bank when GDB is connected and generate proper memory map
 129         halt 1000
 130         if { [esp32s3_memprot_is_enabled] } {
 131                 # 'reset halt' to disable memory protection and allow flasher to work correctly
 132                 echo "Memory protection is enabled. Reset target to disable it..."
 133                 reset halt
 134         }
 135 }
 136 $_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
 137
 138 if { $_ONLYCPU != 1 } {
 139         $_TARGETNAME_1 configure -event gdb-attach {
 140                 $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
 141                 # necessary to auto-probe flash bank when GDB is connected
 142                 halt 1000
 143                 if { [esp32s3_memprot_is_enabled] } {
 144                         # 'reset halt' to disable memory protection and allow flasher to work correctly
 145                         echo "Memory protection is enabled. Reset target to disable it..."
 146                         reset halt
 147                 }
 148         }
 149         $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
 150 }
 151
 152 gdb_breakpoint_override hard
 153
 154 source [find target/xtensa-core-esp32s3.cfg]