tcl/target/esp32s3.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 #
   3 # The ESP32-S3 only supports JTAG.
   4 transport select jtag
   5
   6 set CPU_MAX_ADDRESS 0xFFFFFFFF
   7 source [find bitsbytes.tcl]
   8 source [find memory.tcl]
   9 source [find mmr_helpers.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12         set _CHIPNAME $CHIPNAME
  13 } else {
  14         set _CHIPNAME esp32s3
  15 }
  16
  17 if { [info exists CPUTAPID] } {
  18         set _CPUTAPID $CPUTAPID
  19 } else {
  20         set _CPUTAPID 0x120034e5
  21 }
  22
  23 if { [info exists ESP32_S3_ONLYCPU] } {
  24         set _ONLYCPU $ESP32_S3_ONLYCPU
  25 } else {
  26         set _ONLYCPU 2
  27 }
  28
  29 set _CPU0NAME cpu0
  30 set _CPU1NAME cpu1
  31 set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
  32 set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
  33
  34 jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
  35 if { $_ONLYCPU != 1 } {
  36         jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
  37 } else {
  38         jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
  39 }
  40
  41 proc esp32s3_memprot_is_enabled { } {
  42         # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
  43         if { [get_mmr_bit 0x600C10C0 0] != 0 } {
  44                 return 1
  45         }
  46         # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
  47         if { [get_mmr_bit 0x600C1124 0] != 0 } {
  48                 return 1
  49         }
  50         # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
  51         if { [get_mmr_bit 0x600C11D0 0] != 0 } {
  52                 return 1
  53         }
  54         # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
  55         if { [get_mmr_bit 0x600C10D8 0] != 0 } {
  56                 return 1
  57         }
  58         # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
  59         if { [get_mmr_bit 0x600C10FC 0] != 0 } {
  60                 return 1
  61         }
  62         # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
  63         if { [get_mmr_bit 0x600C10E4 0] != 0 } {
  64                 return 1
  65         }
  66         # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
  67         if { [get_mmr_bit 0x600C10F0 0] != 0 } {
  68                 return 1
  69         }
  70         # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
  71         if { [get_mmr_bit 0x600C1104 0] != 0 } {
  72                 return 1
  73         }
  74         # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
  75         if { [get_mmr_bit 0x600C1114 0] != 0 } {
  76                 return 1
  77         }
  78         # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
  79         if { [get_mmr_bit 0x600C119C 0] != 0 } {
  80                 return 1
  81         }
  82         # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
  83         if { [get_mmr_bit 0x600C1248 0] != 0 } {
  84                 return 1
  85         }
  86         return 0
  87 }
  88
  89 # PRO-CPU
  90 target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
  91 # APP-CPU
  92 if { $_ONLYCPU != 1 } {
  93         target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
  94         target smp $_TARGETNAME_0 $_TARGETNAME_1
  95 }
  96
  97 $_TARGETNAME_0 xtensa maskisr on
  98 $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
  99
 100 $_TARGETNAME_0 configure -event gdb-attach {
 101         $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
 102         # necessary to auto-probe flash bank when GDB is connected and generate proper memory map
 103         halt 1000
 104         if { [esp32s3_memprot_is_enabled] } {
 105                 # 'reset halt' to disable memory protection and allow flasher to work correctly
 106                 echo "Memory protection is enabled. Reset target to disable it..."
 107                 reset halt
 108         }
 109 }
 110 $_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
 111
 112 if { $_ONLYCPU != 1 } {
 113         $_TARGETNAME_1 configure -event gdb-attach {
 114                 $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
 115                 # necessary to auto-probe flash bank when GDB is connected
 116                 halt 1000
 117                 if { [esp32s3_memprot_is_enabled] } {
 118                         # 'reset halt' to disable memory protection and allow flasher to work correctly
 119                         echo "Memory protection is enabled. Reset target to disable it..."
 120                         reset halt
 121                 }
 122         }
 123         $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
 124 }
 125
 126 gdb_breakpoint_override hard