tcl/target/geehy/apm32f1x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Geehy APM32F1x target
   5 #
   6 # https://global.geehy.com/MCU
   7 #
   8
   9 #
  10 # APM32F1x devices support JTAG and SWD transport.
  11 #
  12 source [find target/swj-dp.tcl]
  13
  14 if { [info exists CHIPNAME] } {
  15    set _CHIPNAME $CHIPNAME
  16 } else {
  17    set _CHIPNAME apm32f1x
  18 }
  19
  20 # Work-area is a space in RAM used for flash programming, by default use 4 KiB.
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x1000
  25 }
  26
  27 if { [info exists CPUTAPID] } {
  28    set _CPUTAPID $CPUTAPID
  29 } else {
  30    if { [using_jtag] } {
  31       set _CPUTAPID 0x4ba00477
  32    } {
  33       set _CPUTAPID 0x2ba01477
  34    }
  35 }
  36
  37 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  38 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  39
  40 if {[using_jtag]} {
  41    jtag newtap $_CHIPNAME bs -irlen 5
  42 }
  43
  44 set _TARGETNAME $_CHIPNAME.cpu
  45 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  46
  47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  48
  49 set _FLASHNAME $_CHIPNAME.flash
  50 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
  51
  52 adapter speed 1000
  53
  54 if {![using_hla]} {
  55    # if srst is not fitted use SYSRESETREQ to perform a soft reset.
  56    cortex_m reset_config sysresetreq
  57 }