tcl/target/imx6sx.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Freescale i.MX6SoloX
   5 #
   6
   7 if { [info exists CHIPNAME] } {
   8     set _CHIPNAME $CHIPNAME
   9 } else {
  10     set _CHIPNAME imx6sx
  11 }
  12
  13 # 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
  14 if { [info exists DAP_TAPID] } {
  15     set _DAP_TAPID $DAP_TAPID
  16 } else {
  17     set _DAP_TAPID 0x4ba00477
  18 }
  19
  20 jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
  21         -expected-id $_DAP_TAPID
  22 dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
  23
  24 jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
  25         -expected-id $_DAP_TAPID
  26 dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
  27
  28 # SDMA / no IDCODE
  29 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
  30
  31 # System JTAG Controller
  32 if { [info exists SJC_TAPID] } {
  33     set _SJC_TAPID $SJC_TAPID
  34 } else {
  35     set _SJC_TAPID 0x0891c01d
  36 }
  37 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
  38         -expected-id $_SJC_TAPID -ignore-version
  39
  40 # Cortex-A9 (boot core)
  41 target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
  42         -coreid 0 -dbgbase 0x82150000
  43
  44 # Cortex-M4 (default off)
  45 target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
  46         -ap-num 0 -defer-examine
  47
  48 # AHB mem-ap target
  49 target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
  50
  51 # Default target is Cortex-A9
  52 targets $_CHIPNAME.cpu_a9