1 source [find target/swj-dp.tcl]
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
14 if { [info exists M4_JTAG_TAPID] } {
15 set _M4_JTAG_TAPID $M4_JTAG_TAPID
17 set _M4_JTAG_TAPID 0x4ba00477
23 if { [info exists M4_SWD_TAPID] } {
24 set _M4_SWD_TAPID $M4_SWD_TAPID
26 set _M4_SWD_TAPID 0x2ba01477
30 set _M4_TAPID $_M4_JTAG_TAPID
32 set _M4_TAPID $_M4_SWD_TAPID
38 if { [info exists M0_JTAG_TAPID] } {
39 set _M0_JTAG_TAPID $M0_JTAG_TAPID
41 set _M0_JTAG_TAPID 0x0ba01477
44 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
45 -expected-id $_M4_TAPID
46 target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
49 swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
50 -expected-id $_M0_JTAG_TAPID
51 target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
55 # on this CPU we should use VECTRESET to perform a soft reset and
56 # manually reset the periphery
57 # SRST or SYSRESETREQ disable the debug interface for the time of
58 # the reset and will not fit our requirements for a consistent debug
60 cortex_m reset_config vectreset
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