ipdbg: fix double free of virtual-ir data
[openocd.git] / tcl / target / lsch3_common.cfg
1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # This contains common configuration for NXP Layerscape chassis generation 3
3
4 if { ![info exists _CPUS] } {
5 error "_CPUS must be set to the number of cores"
6 }
7
8 jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
9 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
10
11 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
12
13 set _CPU_BASE 0x81000000
14 set _CPU_STRIDE 0x100000
15 set _CPU_DBGOFF 0x10000
16 set _CPU_CTIOFF 0x20000
17
18 set _TARGETS {}
19 for {set i 0} {$i < $_CPUS} {incr i} {
20 set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
21 cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
22 -baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
23 target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
24 -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
25 {*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
26 lappend _TARGETS $_CHIPNAME.cpu$i
27 }
28
29 target smp {*}$_TARGETS
30
31 # Service processor
32 target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
33
34 # Normally you will not need to call this, but if you are using the hard-coded
35 # Reset Configuration Word (RCW) you will need to call this manually. The CPU's
36 # reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
37 # instructions. This will cause the CPU to almost immediately execute an
38 # illegal instruction.
39 #
40 # This code is idempotent; releasing a released CPU has no effect, although it
41 # will halt/resume the service processor.
42 add_help_text release_cpu "Release a cpu which is held off"
43 proc release_cpu {cpu} {
44 set RST_BRRL 0x1e60060
45
46 set old [target current]
47 targets $::_CHIPNAME.sp
48 set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
49 if {$not_halted} {
50 halt
51 }
52
53 # Release the cpu; it will start executing something bogus
54 mem2array regs 32 $RST_BRRL 1
55 mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
56
57 if {$not_halted} {
58 resume
59 }
60 targets $old
61 }
62
63 targets $_CHIPNAME.cpu0

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)