tcl/target/qn908x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # NXP QN908x Cortex-M4F with 128 KiB SRAM
   4
   5 source [find target/swj-dp.tcl]
   6
   7 set CHIPNAME qn908x
   8 set CHIPSERIES qn9080
   9 if { ![info exists WORKAREASIZE] } {
  10   set WORKAREASIZE 0x20000
  11 }
  12
  13 # SWD IDCODE (Cortex M4).
  14 set CPUTAPID 0x2ba01477
  15
  16 swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
  17 dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu
  18
  19 set TARGETNAME $CHIPNAME.cpu
  20 target create $TARGETNAME cortex_m -dap $CHIPNAME.dap
  21
  22 # SRAM is mapped at 0x04000000.
  23 $TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE
  24
  25 # flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum]
  26 # The base must be set as 0x01000000, and the size parameter is unused.
  27 set FLASHNAME $CHIPNAME.flash
  28 flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
  29
  30 # We write directly to flash memory over this adapter interface. For debugging
  31 # this could in theory be faster (the Core clock on reset is normally at 32MHz),
  32 # but for flashing 1MHz is more reliable.
  33 adapter speed 1000
  34
  35 # Delay on reset line.
  36 adapter srst delay 200
  37
  38 cortex_m reset_config sysresetreq