tcl/target/stm32f7x.cfg

   1 # script for stm32f7x family
   2
   3 #
   4 # stm32f7 devices support both JTAG and SWD transports.
   5 #
   6 source [find target/swj-dp.tcl]
   7 source [find mem_helper.tcl]
   8
   9 if { [info exists CHIPNAME] } {
  10    set _CHIPNAME $CHIPNAME
  11 } else {
  12    set _CHIPNAME stm32f7x
  13 }
  14
  15 set _ENDIAN little
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 128kB
  19 if { [info exists WORKAREASIZE] } {
  20    set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22    set _WORKAREASIZE 0x20000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27    set _CPUTAPID $CPUTAPID
  28 } else {
  29    if { [using_jtag] } {
  30       # See STM Document RM0385
  31       # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
  32       set _CPUTAPID 0x5ba00477
  33    } {
  34       set _CPUTAPID 0x5ba02477
  35    }
  36 }
  37
  38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  40
  41 if {[using_jtag]} {
  42    jtag newtap $_CHIPNAME bs -irlen 5
  43 }
  44
  45 set _TARGETNAME $_CHIPNAME.cpu
  46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
  47
  48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  49
  50 set _FLASHNAME $_CHIPNAME.flash
  51 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
  52 flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
  53
  54 # On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
  55 # also address 0x00200000 via the ITCM. The former mapping is read-write in
  56 # hardware, while the latter is read-only. By presenting an alias, we
  57 # accomplish two things:
  58 # (1) We allow writing at 0x00200000 (because the alias acts identically to the
  59 #     original bank), which allows code intended to run from that address to
  60 #     also be linked for loading at that address, simplifying linking.
  61 # (2) We allow the proper memory map to be delivered to GDB, which will cause
  62 #     it to use hardware breakpoints at the 0x00200000 mapping (correctly
  63 #     identifying it as Flash), which it would otherwise not do. Configuring
  64 #     the Flash via ITCM alias as virtual
  65 flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
  66
  67 if { [info exists QUADSPI] && $QUADSPI } {
  68    set a [llength [flash list]]
  69    set _QSPINAME $_CHIPNAME.qspi
  70    flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
  71 }
  72
  73 # adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
  74 adapter speed 2000
  75
  76 adapter srst delay 100
  77 if {[using_jtag]} {
  78  jtag_ntrst_delay 100
  79 }
  80
  81 # Use hardware reset.
  82 #
  83 # This target is compatible with connect_assert_srst, which may be set in a
  84 # board file.
  85 reset_config srst_nogate
  86
  87 if {![using_hla]} {
  88    # if srst is not fitted use SYSRESETREQ to
  89    # perform a soft reset
  90    cortex_m reset_config sysresetreq
  91
  92    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
  93    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
  94    # makes the data access cacheable. This allows reading and writing data in the
  95    # CPU cache from the debugger, which is far more useful than going straight to
  96    # RAM when operating on typical variables, and is generally no worse when
  97    # operating on special memory locations.
  98    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
  99 }
 100
 101 $_TARGETNAME configure -event examine-end {
 102         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
 103         mmw 0xE0042004 0x00000007 0
 104
 105         # Stop watchdog counters during halt
 106         # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
 107         mmw 0xE0042008 0x00001800 0
 108 }
 109
 110 $_TARGETNAME configure -event trace-config {
 111         # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
 112         # change this value accordingly to configure trace pins
 113         # assignment
 114         mmw 0xE0042004 0x00000020 0
 115 }
 116
 117 $_TARGETNAME configure -event reset-init {
 118         # If the HSE was previously enabled and the external clock source
 119         # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
 120         # properly switched back to HSI. This situation persists even over a system
 121         # reset, including a pin reset via SRST. However, activating the clock
 122         # security system will detect the problem and clear HSERDY to 0, which in
 123         # turn allows the PLL to switch back to HSI properly. Since we just came
 124         # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
 125         # have happened; in that case, activate the clock security system to clear
 126         # HSERDY.
 127         if {[mrw 0x40023800] & 0x00020000} {
 128                 mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
 129                 sleep 10                    ;# Wait for CSS to fire, if it wants to
 130                 mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
 131                 mww 0x4002380C 0x00800000   ;# RCC_CIR = CSSC
 132                 sleep 1                     ;# Wait for CSSF to clear
 133         }
 134
 135         # If the clock security system fired, it will pend an NMI. A pending NMI
 136         # will cause a bad time for any subsequent executing code, such as a
 137         # programming algorithm.
 138         if {[mrw 0xE000ED04] & 0x80000000} {
 139                 # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
 140                 # cleared by any normal means (such as ICSR or NVIC). It can only be
 141                 # cleared by entering the NMI handler or by resetting the processor.
 142                 echo "[target current]: Clock security system generated NMI. Clearing."
 143
 144                 # Keep the old DEMCR value.
 145                 set old [mrw 0xE000EDFC]
 146
 147                 # Enable vector catch on reset.
 148                 mww 0xE000EDFC 0x01000001
 149
 150                 # Issue local reset via AIRCR.
 151                 mww 0xE000ED0C 0x05FA0001
 152
 153                 # Restore old DEMCR value.
 154                 mww 0xE000EDFC $old
 155         }
 156
 157         # Configure PLL to boost clock to HSI x 10 (160 MHz)
 158         mww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
 159         mww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)
 160         mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
 161         sleep 10                    ;# Wait for PLL to lock
 162         mww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
 163         mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
 164
 165         # Boost SWD frequency
 166         # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
 167         # suffers from DAP WAITs
 168         if {[using_jtag]} {
 169                 [[target current] cget -dap] memaccess 16
 170         } {
 171                 adapter speed 8000
 172         }
 173 }
 174
 175 $_TARGETNAME configure -event reset-start {
 176         # Reduce speed since CPU speed will slow down to 16MHz with the reset
 177         adapter speed 2000
 178 }