tcl/target/stm32h7x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32h7x family
   4
   5 #
   6 # stm32h7 devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12    set _CHIPNAME $CHIPNAME
  13 } else {
  14    set _CHIPNAME stm32h7x
  15 }
  16
  17 if { [info exists DUAL_BANK] } {
  18         set $_CHIPNAME.DUAL_BANK $DUAL_BANK
  19         unset DUAL_BANK
  20 } else {
  21         set $_CHIPNAME.DUAL_BANK 0
  22 }
  23
  24 if { [info exists DUAL_CORE] } {
  25         set $_CHIPNAME.DUAL_CORE $DUAL_CORE
  26         unset DUAL_CORE
  27 } else {
  28         set $_CHIPNAME.DUAL_CORE 0
  29 }
  30
  31 # Issue a warning when hla is used, and fallback to single core configuration
  32 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
  33         echo "Warning : hla does not support multicore debugging"
  34         set $_CHIPNAME.DUAL_CORE 0
  35 }
  36
  37 if { [info exists USE_CTI] } {
  38         set $_CHIPNAME.USE_CTI $USE_CTI
  39         unset USE_CTI
  40 } else {
  41         set $_CHIPNAME.USE_CTI 0
  42 }
  43
  44 # Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
  45 if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
  46         echo "Warning : could not use CTI with a single core device, CTI is disabled"
  47         set $_CHIPNAME.USE_CTI 0
  48 }
  49
  50 set _ENDIAN little
  51
  52 # Work-area is a space in RAM used for flash programming
  53 # By default use 64kB
  54 if { [info exists WORKAREASIZE] } {
  55    set _WORKAREASIZE $WORKAREASIZE
  56 } else {
  57    set _WORKAREASIZE 0x10000
  58 }
  59
  60 #jtag scan chain
  61 if { [info exists CPUTAPID] } {
  62    set _CPUTAPID $CPUTAPID
  63 } else {
  64    if { [using_jtag] } {
  65           set _CPUTAPID 0x6ba00477
  66    } {
  67       set _CPUTAPID 0x6ba02477
  68    }
  69 }
  70
  71 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  72 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  73
  74 if {[using_jtag]} {
  75    jtag newtap $_CHIPNAME bs -irlen 5
  76 }
  77
  78 if {![using_hla]} {
  79         # STM32H7 provides an APB-AP at access port 2, which allows the access to
  80         # the debug and trace features on the system APB System Debug Bus (APB-D).
  81         target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
  82         swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
  83         tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
  84 }
  85
  86 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
  87
  88 $_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  89
  90 flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
  91
  92 if {[set $_CHIPNAME.DUAL_BANK]} {
  93         flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
  94 }
  95
  96 if {[set $_CHIPNAME.DUAL_CORE]} {
  97         target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
  98
  99         $_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 100
 101         flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
 102
 103         if {[set $_CHIPNAME.DUAL_BANK]} {
 104                 flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
 105         }
 106 }
 107
 108 # Make sure that cpu0 is selected
 109 targets $_CHIPNAME.cpu0
 110
 111 if { [info exists QUADSPI] && $QUADSPI } {
 112    set a [llength [flash list]]
 113    set _QSPINAME $_CHIPNAME.qspi
 114    flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
 115 } else {
 116    if { [info exists OCTOSPI1] && $OCTOSPI1 } {
 117       set a [llength [flash list]]
 118       set _OCTOSPINAME1 $_CHIPNAME.octospi1
 119       flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
 120    }
 121    if { [info exists OCTOSPI2] && $OCTOSPI2 } {
 122       set b [llength [flash list]]
 123       set _OCTOSPINAME2 $_CHIPNAME.octospi2
 124       flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
 125    }
 126 }
 127
 128 # Clock after reset is HSI at 64 MHz, no need of PLL
 129 adapter speed 1800
 130
 131 adapter srst delay 100
 132 if {[using_jtag]} {
 133  jtag_ntrst_delay 100
 134 }
 135
 136 # use hardware reset
 137 #
 138 # The STM32H7 does not support connect_assert_srst mode because the AXI is
 139 # unavailable while SRST is asserted, and that is used to access the DBGMCU
 140 # component at 0x5C001000 in the examine-end event handler.
 141 #
 142 # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
 143 # of the default AP0, and that works with SRST asserted; however, nonzero AP
 144 # usage does not work with HLA, so is not done by default. That change could be
 145 # made in a local configuration file if connect_assert_srst mode is needed for
 146 # a specific application and a non-HLA adapter is in use.
 147 reset_config srst_nogate
 148
 149 if {![using_hla]} {
 150    # if srst is not fitted use SYSRESETREQ to
 151    # perform a soft reset
 152         $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
 153
 154         if {[set $_CHIPNAME.DUAL_CORE]} {
 155                 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
 156         }
 157
 158    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
 159    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
 160    # makes the data access cacheable. This allows reading and writing data in the
 161    # CPU cache from the debugger, which is far more useful than going straight to
 162    # RAM when operating on typical variables, and is generally no worse when
 163    # operating on special memory locations.
 164    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 165 }
 166
 167 $_CHIPNAME.cpu0 configure -event examine-end {
 168         # Enable D3 and D1 DBG clocks
 169         # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
 170         stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 171
 172         # Enable debug during low power modes (uses more power)
 173         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
 174         stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
 175         # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
 176         stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
 177
 178         # Stop watchdog counters during halt
 179         # DBGMCU_APB3FZ1 |= WWDG1
 180         stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
 181         # DBGMCU_APB1LFZ1 |= WWDG2
 182         stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
 183         # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
 184         stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
 185
 186         # Enable clock for tracing
 187         # DBGMCU_CR |= TRACECLKEN
 188         stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 189
 190         # RM0399 (id 0x450) M7+M4 with SWO Funnel
 191         # RM0433 (id 0x450) M7 with SWO Funnel
 192         # RM0455 (id 0x480) M7 without SWO Funnel
 193         # RM0468 (id 0x483) M7 without SWO Funnel
 194         # Enable CM7 and CM4 slave ports in SWO trace Funnel
 195         # Works ok also on devices single core and without SWO funnel
 196         # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
 197         # SWTF_CTRL |= ENS0 | ENS1
 198         stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
 199 }
 200
 201 $_CHIPNAME.cpu0 configure -event reset-init {
 202         # Clock after reset is HSI at 64 MHz, no need of PLL
 203         adapter speed 4000
 204 }
 205
 206 # get _CHIPNAME from current target
 207 proc stm32h7x_get_chipname {} {
 208         set t [target current]
 209         set sep [string last "." $t]
 210         if {$sep == -1} {
 211                 return $t
 212         }
 213         return [string range $t 0 [expr {$sep - 1}]]
 214 }
 215
 216 if {[set $_CHIPNAME.DUAL_CORE]} {
 217         $_CHIPNAME.cpu1 configure -event examine-end {
 218                 set _CHIPNAME [stm32h7x_get_chipname]
 219                 global $_CHIPNAME.USE_CTI
 220
 221                 # Stop watchdog counters during halt
 222                 # DBGMCU_APB3FZ2 |= WWDG1
 223                 stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
 224                 # DBGMCU_APB1LFZ2 |= WWDG2
 225                 stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
 226                 # DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
 227                 stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
 228
 229                 if {[set $_CHIPNAME.USE_CTI]} {
 230                         stm32h7x_cti_start
 231                 }
 232         }
 233 }
 234
 235 # like mrw, but with target selection
 236 proc stm32h7x_mrw {used_target reg} {
 237         return [$used_target read_memory $reg 32 1]
 238 }
 239
 240 # like mmw, but with target selection
 241 proc stm32h7x_mmw {used_target reg setbits clearbits} {
 242         set old [stm32h7x_mrw $used_target $reg]
 243         set new [expr {($old & ~$clearbits) | $setbits}]
 244         $used_target mww $reg $new
 245 }
 246
 247 # mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
 248 # this procedure will use the mem_ap on AP2 whenever possible
 249 proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 250         # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
 251         if {![using_hla]} {
 252                 set _CHIPNAME [stm32h7x_get_chipname]
 253                 set used_target $_CHIPNAME.ap2
 254                 set reg_addr [expr {0xE00E1000 + $reg_offset}]
 255         } {
 256                 set used_target [target current]
 257                 set reg_addr [expr {0x5C001000 + $reg_offset}]
 258         }
 259
 260         stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
 261 }
 262
 263 if {[set $_CHIPNAME.USE_CTI]} {
 264         # create CTI instances for both cores
 265         cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
 266         cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
 267
 268         $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
 269         $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
 270
 271         $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
 272         $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
 273
 274         proc stm32h7x_cti_start {} {
 275                 set _CHIPNAME [stm32h7x_get_chipname]
 276
 277                 # Configure Cores' CTIs to halt each other
 278                 # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
 279                 $_CHIPNAME.cti0 write INEN0 0x1
 280                 $_CHIPNAME.cti0 write OUTEN0 0x1
 281                 $_CHIPNAME.cti1 write INEN0 0x1
 282                 $_CHIPNAME.cti1 write OUTEN0 0x1
 283
 284                 # enable CTIs
 285                 $_CHIPNAME.cti0 enable on
 286                 $_CHIPNAME.cti1 enable on
 287         }
 288
 289         proc stm32h7x_cti_stop {} {
 290                 set _CHIPNAME [stm32h7x_get_chipname]
 291
 292                 $_CHIPNAME.cti0 enable off
 293                 $_CHIPNAME.cti1 enable off
 294         }
 295
 296         proc stm32h7x_cti_prepare_restart_all {} {
 297                 stm32h7x_cti_prepare_restart cti0
 298                 stm32h7x_cti_prepare_restart cti1
 299         }
 300
 301         proc stm32h7x_cti_prepare_restart {cti} {
 302                 set _CHIPNAME [stm32h7x_get_chipname]
 303
 304                 # Acknowlodge EDBGRQ at TRIGOUT0
 305                 $_CHIPNAME.$cti write INACK 0x01
 306                 $_CHIPNAME.$cti write INACK 0x00
 307         }
 308 }