tcl/target/stm32mp15x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
   4 # http://www.st.com/stm32mp1
   5
   6 # HLA does not support multi-cores nor custom CSW nor AP other than 0
   7 if { [using_hla] } {
   8         echo "ERROR: HLA transport cannot work with this target."
   9         echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
  10         shutdown
  11 }
  12
  13 source [find target/swj-dp.tcl]
  14
  15 if { [info exists CHIPNAME] } {
  16         set _CHIPNAME $CHIPNAME
  17 } else {
  18         set _CHIPNAME stm32mp15x
  19 }
  20
  21 if { [info exists CPUTAPID] } {
  22         set _CPUTAPID $CPUTAPID
  23 } else {
  24         if { [using_jtag] } {
  25                 set _CPUTAPID 0x6ba00477
  26         } else {
  27                 set _CPUTAPID 0x6ba02477
  28         }
  29 }
  30
  31 # Chip Level TAP Controller, only in jtag mode
  32 if { [info exists CLCTAPID] } {
  33         set _CLCTAPID $CLCTAPID
  34 } else {
  35         set _CLCTAPID 0x06500041
  36 }
  37
  38 swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
  39 if { [using_jtag] } {
  40         jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
  41 }
  42
  43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
  44
  45 # FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
  46 # so defer-examine it until the reset framework get merged
  47 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
  48 # NOTE: do not change the order of target create
  49 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
  50 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
  51 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
  52 target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
  53 target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
  54 target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
  55
  56 targets $_CHIPNAME.cpu0
  57
  58 target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
  59 $_CHIPNAME.cpu0 cortex_a maskisr on
  60 $_CHIPNAME.cpu1 cortex_a maskisr on
  61 $_CHIPNAME.cpu0 cortex_a dacrfixup on
  62 $_CHIPNAME.cpu1 cortex_a dacrfixup on
  63
  64 cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
  65 cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
  66 cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
  67 cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
  68
  69 swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
  70 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
  71
  72 # interface does not work while srst is asserted
  73 # this is target specific, valid for every board
  74 # Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
  75 # srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
  76 # debug unit, behavior equivalent to "srst_pulls_trst"
  77 reset_config srst_gates_jtag srst_pulls_trst
  78
  79 adapter speed 5000
  80 adapter srst pulse_width 200
  81 # bootrom has an internal timeout of 1 second for detecting the boot flash.
  82 # wait at least 1 second to guarantee we are out of bootrom
  83 adapter srst delay 1100
  84
  85 add_help_text axi_secure "Set secure mode for following AXI accesses"
  86 proc axi_secure {} {
  87         $::_CHIPNAME.dap apsel 0
  88         $::_CHIPNAME.dap apcsw 0x10006000
  89 }
  90
  91 add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
  92 proc axi_nsecure {} {
  93         $::_CHIPNAME.dap apsel 0
  94         $::_CHIPNAME.dap apcsw 0x30006000
  95 }
  96
  97 axi_secure
  98
  99 proc dbgmcu_enable_debug {} {
 100         # set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 101         catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
 102         # freeze watchdog 1 and 2 on cores halted
 103         catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
 104         catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 105 }
 106
 107 proc toggle_cpu0_dbg_claim0 {} {
 108         # toggle CPU0 DBG_CLAIM[0]
 109         $::_CHIPNAME.ap1 mww 0xe00d0fa0 1
 110         $::_CHIPNAME.ap1 mww 0xe00d0fa4 1
 111 }
 112
 113 proc detect_cpu1 {} {
 114         set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
 115         set dual_core [expr {$cpu1_prsr & 1}]
 116         if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
 117 }
 118
 119 proc rcc_enable_traceclk {} {
 120         $::_CHIPNAME.ap2 mww 0x5000080c 0x301
 121 }
 122
 123 # FIXME: most of handler below will be removed once reset framework get merged
 124 $_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
 125 $_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 126 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 127 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
 128 $_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
 129 $_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
 130 $_CHIPNAME.ap1  configure -event examine-start       {dap init}
 131 $_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
 132 $_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
 133 $_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}