tcl/cpld: add config files for more xilinx fpga families
[openocd.git] / tcl / target / str750.cfg
1 # SPDX-License-Identifier: GPL-2.0-or-later
2
3 #STR750 CPU
4
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
7 } else {
8 set _CHIPNAME str750
9 }
10
11 if { [info exists ENDIAN] } {
12 set _ENDIAN $ENDIAN
13 } else {
14 set _ENDIAN little
15 }
16
17 if { [info exists CPUTAPID] } {
18 set _CPUTAPID $CPUTAPID
19 } else {
20 set _CPUTAPID 0x4f1f0041
21 }
22
23 # jtag speed
24 adapter speed 10
25
26 #use combined on interfaces or targets that can't set TRST/SRST separately
27 reset_config trst_and_srst srst_pulls_trst
28
29 #jtag scan chain
30
31 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
32
33 #jtag nTRST and nSRST delay
34 adapter srst delay 500
35 jtag_ntrst_delay 500
36
37 set _TARGETNAME $_CHIPNAME.cpu
38 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
39
40 $_TARGETNAME configure -event reset-start { adapter speed 10 }
41 $_TARGETNAME configure -event reset-init {
42 adapter speed 3000
43
44 init_smi
45 # Because the hardware cannot be interrogated for the protection state
46 # of sectors, initialize all the sectors to be unprotected. The initial
47 # state is reflected by the driver, too.
48 flash protect 0 0 last off
49 flash protect 1 0 last off
50 }
51 $_TARGETNAME configure -event gdb-flash-erase-start {
52 flash protect 0 0 7 off
53 flash protect 1 0 1 off
54 }
55
56 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
57
58 #flash bank <driver> <base> <size> <chip_width> <bus_width>
59 set _FLASHNAME $_CHIPNAME.flash0
60 flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
61 set _FLASHNAME $_CHIPNAME.flash1
62 flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
63
64 # Serial NOR on SMI CS0.
65 set _FLASHNAME $_CHIPNAME.snor
66 flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME
67
68 source [find mem_helper.tcl]
69
70 proc init_smi {} {
71 mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
72 mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
73 mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1
74 }

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