tcl/target/ti_dm6446.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Texas Instruments DaVinci family: TMS320DM6446
   5 #
   6 if { [info exists CHIPNAME] } {
   7    set _CHIPNAME $CHIPNAME
   8 } else {
   9    set _CHIPNAME dm6446
  10 }
  11
  12 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
  13 # after JTAG reset until ICEpick is used to route them in.
  14 set EMU01 "-disable"
  15
  16 # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
  17 # needing any ICEpick interaction.
  18 #set EMU01 "-enable"
  19
  20 source [find target/icepick.cfg]
  21
  22 # Subsidiary TAP: unknown ... must enable via ICEpick
  23 jtag newtap $_CHIPNAME unknown -irlen 8 -disable
  24 jtag configure $_CHIPNAME.unknown -event tap-enable \
  25         "icepick_c_tapenable $_CHIPNAME.jrc 3"
  26
  27 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
  28 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
  29 jtag configure $_CHIPNAME.dsp -event tap-enable \
  30         "icepick_c_tapenable $_CHIPNAME.jrc 2"
  31
  32 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
  33 if { [info exists ETB_TAPID] } {
  34    set _ETB_TAPID $ETB_TAPID
  35 } else {
  36    set _ETB_TAPID 0x2b900f0f
  37 }
  38 jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
  39 jtag configure $_CHIPNAME.etb -event tap-enable \
  40         "icepick_c_tapenable $_CHIPNAME.jrc 1"
  41
  42 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
  43 if { [info exists CPU_TAPID] } {
  44    set _CPU_TAPID $CPU_TAPID
  45 } else {
  46    set _CPU_TAPID 0x07926001
  47 }
  48 jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
  49 jtag configure $_CHIPNAME.arm -event tap-enable \
  50         "icepick_c_tapenable $_CHIPNAME.jrc 0"
  51
  52 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
  53 if { [info exists JRC_TAPID] } {
  54    set _JRC_TAPID $JRC_TAPID
  55 } else {
  56    set _JRC_TAPID 0x0b70002f
  57 }
  58 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
  59
  60 jtag configure $_CHIPNAME.jrc -event setup \
  61         "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
  62
  63 ################
  64 # GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
  65 # and the ETB memory (4K) are other options, while trace is unused.
  66 # Little-endian; use the OpenOCD default.
  67 set _TARGETNAME $_CHIPNAME.arm
  68
  69 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
  70 $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
  71
  72 # be absolutely certain the JTAG clock will work with the worst-case
  73 # CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
  74 # on the PLL and starts using it.  OK to speed up after clock setup.
  75 adapter speed 1500
  76 $_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
  77
  78 arm7_9 fast_memory_access enable
  79 arm7_9 dcc_downloads enable
  80
  81 # trace setup
  82 etm config $_TARGETNAME 16 normal full etb
  83 etb config $_TARGETNAME $_CHIPNAME.etb