1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
6 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
7 # * J721E: https://www.ti.com/lit/pdf/spruil1
8 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
10 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
11 # * AM642: https://www.ti.com/lit/pdf/spruim2
12 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
15 source [find target/swj-dp.tcl]
17 if { [info exists SOC] } {
23 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
24 if { [info exists V8_SMP_DEBUG] } {
25 set _v8_smp_debug $V8_SMP_DEBUG
32 # System Controller is the very first processor - all current SoCs have it.
33 set CM3_CTIBASE {0x3C016000}
35 # sysctrl power-ap unlock offsets
36 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
38 # All the ARMV8s are the next processors.
39 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
40 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
41 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
43 # And we add up the R5s
44 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
45 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
46 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
47 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
49 # Finally an General Purpose(GP) MCU
50 set CM4_CTIBASE {0x20001000}
52 # General Purpose MCU (M4) may be present on some very few SoCs
54 # General Purpose MCU power-ap unlock offsets
55 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
57 # Set configuration overrides for each SOC
61 set _K3_DAP_TAPID 0x0bb5a02f
63 # AM654 has 2 clusters of 2 A53 cores each.
64 set _armv8_cpu_name a53
67 # AM654 has 1 cluster of 2 R5s cores.
69 set R5_NAMES {mcu_r5.0 mcu_r5.1}
71 # Sysctrl power-ap unlock offsets
72 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
76 set _K3_DAP_TAPID 0x0bb3802f
78 # AM642 has 1 clusters of 2 A53 cores each.
79 set _armv8_cpu_name a53
81 set ARMV8_DBGBASE {0x90010000 0x90110000}
82 set ARMV8_CTIBASE {0x90020000 0x90120000}
84 # AM642 has 2 cluster of 2 R5s cores.
86 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
87 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
88 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
95 set _K3_DAP_TAPID 0x0bb7e02f
97 # AM625 has 1 clusters of 4 A53 cores.
98 set _armv8_cpu_name a53
100 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
101 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
103 # AM625 has 1 cluster of 1 R5s core.
105 set R5_NAMES {main0_r5.0}
106 set R5_DBGBASE {0x9d410000}
107 set R5_CTIBASE {0x9d418000}
110 set CM3_CTIBASE {0x20001000}
111 # Sysctrl power-ap unlock offsets
112 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
116 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
120 set _K3_DAP_TAPID 0x0bb6402f
121 # J721E has 1 cluster of 2 A72 cores.
122 set _armv8_cpu_name a72
125 # J721E has 3 clusters of 2 R5 cores each.
130 set _K3_DAP_TAPID 0x0bb6d02f
132 # J7200 has 1 cluster of 2 A72 cores.
133 set _armv8_cpu_name a72
136 # J7200 has 2 clusters of 2 R5 cores each.
138 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
139 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
142 set CM3_CTIBASE {0x20001000}
146 set _K3_DAP_TAPID 0x0bb7502f
148 # J721s2 has 1 cluster of 2 A72 cores.
149 set _armv8_cpu_name a72
152 # J721s2 has 3 clusters of 2 R5 cores each.
156 set CM3_CTIBASE {0x20001000}
157 # Sysctrl power-ap unlock offsets
158 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
162 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
165 echo "'$_soc' is invalid!"
169 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
171 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
173 set _TARGETNAME $_CHIPNAME.cpu
175 set _CTINAME $_CHIPNAME.cti
177 # sysctrl is always present
178 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
179 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
180 $_TARGETNAME.sysctrl configure -event reset-assert { }
183 # To access sysctrl, we need to enable the JTAG access for the same.
184 # Ensure Power-AP unlocked
185 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
186 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
188 $::_TARGETNAME.sysctrl arp_examine
191 $_TARGETNAME.sysctrl configure -event gdb-attach {
193 # gdb-attach default rule
197 proc _cpu_no_smp_up {} {
198 set _current_target [target current]
199 set _current_type [$_current_target cget -type]
201 $_current_target arp_examine
202 $_current_target $_current_type dbginit
205 proc _armv8_smp_up {} {
206 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
207 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
208 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
209 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
211 # Set Default target as core 0
212 targets $::_TARGETNAME.$::_armv8_cpu_name.0
215 set _v8_smp_targets ""
217 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
219 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
220 -baseaddr [lindex $ARMV8_CTIBASE $_core]
222 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
223 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
225 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
227 if { $_v8_smp_debug == 0 } {
228 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
230 # gdb-attach default rule
234 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
236 # gdb-attach default rule
242 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
243 set _armv8_up_cmd "$_armv8_cpu_name"_up
244 # Available if V8_SMP_DEBUG is set to non-zero value
245 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
247 if { $_v8_smp_debug == 0 } {
248 proc $_armv8_up_cmd { args } {
249 foreach _core $args {
255 proc $_armv8_smp_cmd { args } {
259 target smp $:::_v8_smp_targets
262 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
263 set _r5_name [lindex $R5_NAMES $_core]
264 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
265 -baseaddr [lindex $R5_CTIBASE $_core]
267 # inactive core examination will fail - wait till startup of additional core
268 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
269 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
271 $_TARGETNAME.$_r5_name configure -event gdb-attach {
273 # gdb-attach default rule
278 proc r5_up { args } {
279 foreach _core $args {
285 if { $_gp_mcu_cores != 0 } {
286 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
287 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
288 $_TARGETNAME.gp_mcu configure -event reset-assert { }
291 # To access GP MCU, we need to enable the JTAG access for the same.
292 # Ensure Power-AP unlocked
293 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
294 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
296 $::_TARGETNAME.gp_mcu arp_examine
299 $_TARGETNAME.gp_mcu configure -event gdb-attach {
301 # gdb-attach default rule