1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
6 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
7 # * J721E: https://www.ti.com/lit/pdf/spruil1
8 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
10 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
11 # * J721S2: https://www.ti.com/lit/pdf/spruj28
12 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
13 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
14 # Has 8 ARMV8 Cores and 8 R5 Cores
15 # * AM642: https://www.ti.com/lit/pdf/spruim2
16 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
17 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
18 # Has 4 ARMV8 Cores and 1 R5 Core and an M4F
19 # * AM62a7: https://www.ti.com/lit/pdf/spruj16a
20 # Has 4 ARMV8 Cores and 2 R5 Cores
21 # * AM62P: https://www.ti.com/lit/pdf/spruj83
22 # Has 4 ARMV8 Cores and 2 R5 Cores
25 source [find target/swj-dp.tcl]
27 if { [info exists SOC] } {
33 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
34 if { [info exists V8_SMP_DEBUG] } {
35 set _v8_smp_debug $V8_SMP_DEBUG
42 # System Controller is the very first processor - all current SoCs have it.
43 set CM3_CTIBASE {0x3C016000}
45 # sysctrl power-ap unlock offsets
46 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
49 # All the ARMV8s are the next processors.
50 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
51 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
52 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
54 # And we add up the R5s
55 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
56 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
57 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
58 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
61 # Finally an General Purpose(GP) MCU
62 set CM4_CTIBASE {0x20001000}
64 # General Purpose MCU (M4) may be present on some very few SoCs
66 # General Purpose MCU power-ap unlock offsets
67 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
69 # Generic mem-ap port number
72 # Set configuration overrides for each SOC
75 set _K3_DAP_TAPID 0x0bb5a02f
77 # AM654 has 2 clusters of 2 A53 cores each.
78 set _armv8_cpu_name a53
81 # AM654 has 1 cluster of 2 R5s cores.
83 set R5_NAMES {mcu_r5.0 mcu_r5.1}
85 # Sysctrl power-ap unlock offsets
86 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
89 set _K3_DAP_TAPID 0x0bb3802f
91 # AM642 has 1 clusters of 2 A53 cores each.
92 set _armv8_cpu_name a53
94 set ARMV8_DBGBASE {0x90010000 0x90110000}
95 set ARMV8_CTIBASE {0x90020000 0x90120000}
97 # AM642 has 2 cluster of 2 R5s cores.
99 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
100 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
101 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
107 set _K3_DAP_TAPID 0x0bb7e02f
109 # AM625 has 1 clusters of 4 A53 cores.
110 set _armv8_cpu_name a53
112 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
113 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
115 # AM625 has 1 cluster of 1 R5s core.
117 set R5_NAMES {main0_r5.0}
118 set R5_DBGBASE {0x9d410000}
119 set R5_CTIBASE {0x9d418000}
122 set CM3_CTIBASE {0x20001000}
123 # Sysctrl power-ap unlock offsets
124 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
128 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
130 # Setup DMEM access descriptions
131 # DAPBUS (Debugger) description
132 set _dmem_base_address 0x740002000
133 set _dmem_ap_address_offset 0x100
135 # Emulated AP description
136 set _dmem_emu_base_address 0x760000000
137 set _dmem_emu_base_address_map_to 0x1d500000
138 set _dmem_emu_ap_list 1
142 set _K3_DAP_TAPID 0x0bb8d02f
144 # AM62a7/AM62P has 1 cluster of 4 A53 cores.
145 set _armv8_cpu_name a53
147 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
148 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
150 # AM62a7/AM62P has 2 cluster of 1 R5 core.
152 set R5_NAMES {main0_r5.0 mcu0_r5.0}
153 set R5_DBGBASE {0x9d410000 0x9d810000}
154 set R5_CTIBASE {0x9d418000 0x9d818000}
157 set CM3_CTIBASE {0x20001000}
158 # Sysctrl power-ap unlock offsets
159 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
161 # Overrides for am62p
162 if { "$_soc" == "am62p" } {
163 set _K3_DAP_TAPID 0x0bb9d02f
164 set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
168 set _K3_DAP_TAPID 0x0bb6402f
169 # J721E has 1 cluster of 2 A72 cores.
170 set _armv8_cpu_name a72
173 # J721E has 3 clusters of 2 R5 cores each.
176 # Setup DMEM access descriptions
177 # DAPBUS (Debugger) description
178 set _dmem_base_address 0x4c40002000
179 set _dmem_ap_address_offset 0x100
181 # Emulated AP description
182 set _dmem_emu_base_address 0x4c60000000
183 set _dmem_emu_base_address_map_to 0x1d600000
184 set _dmem_emu_ap_list 1
187 set _K3_DAP_TAPID 0x0bb6d02f
189 # J7200 has 1 cluster of 2 A72 cores.
190 set _armv8_cpu_name a72
193 # J7200 has 2 clusters of 2 R5 cores each.
195 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
196 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
199 set CM3_CTIBASE {0x20001000}
202 set _K3_DAP_TAPID 0x0bb7502f
204 # J721s2 has 1 cluster of 2 A72 cores.
205 set _armv8_cpu_name a72
208 # J721s2 has 3 clusters of 2 R5 cores each.
212 set CM3_CTIBASE {0x20001000}
213 # Sysctrl power-ap unlock offsets
214 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
218 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
221 set _K3_DAP_TAPID 0x0bb8002f
223 # j784s4 has 2 cluster of 4 A72 cores each.
224 set _armv8_cpu_name a72
226 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
227 0x90810000 0x90910000 0x90a10000 0x90b10000}
228 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
229 0x90820000 0x90920000 0x90a20000 0x90b20000}
231 # J721s2 has 4 clusters of 2 R5 cores each.
233 set R5_DBGBASE {0x9d010000 0x9d012000
234 0x9d410000 0x9d412000
235 0x9d510000 0x9d512000
236 0x9d610000 0x9d612000}
237 set R5_CTIBASE {0x9d018000 0x9d019000
238 0x9d418000 0x9d419000
239 0x9d518000 0x9d519000
240 0x9d618000 0x9d619000}
241 set R5_NAMES {mcu_r5.0 mcu_r5.1
242 main0_r5.0 main0_r5.1
243 main1_r5.0 main1_r5.1
244 main2_r5.0 main2_r5.1}
247 set CM3_CTIBASE {0x20001000}
248 # Sysctrl power-ap unlock offsets
249 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
252 echo "'$_soc' is invalid!"
256 proc _get_rtos_type_for_cpu { target_name } {
257 if { [info exists ::RTOS($target_name)] } {
258 return $::RTOS($target_name)
265 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
267 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
269 set _TARGETNAME $_CHIPNAME.cpu
271 set _CTINAME $_CHIPNAME.cti
273 # sysctrl is always present
274 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
275 -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
277 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
278 -ap-num $_sysctrl_ap_num -defer-examine \
279 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
281 $_TARGETNAME.sysctrl configure -event reset-assert { }
284 # To access sysctrl, we need to enable the JTAG access for the same.
285 # Ensure Power-AP unlocked
286 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
287 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
289 $::_TARGETNAME.sysctrl arp_examine
292 $_TARGETNAME.sysctrl configure -event gdb-attach {
294 # gdb-attach default rule
298 proc _cpu_no_smp_up {} {
299 set _current_target [target current]
300 set _current_type [$_current_target cget -type]
302 $_current_target arp_examine
303 $_current_target $_current_type dbginit
306 proc _armv8_smp_up {} {
307 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
308 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
309 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
310 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
312 # Set Default target as core 0
313 targets $::_TARGETNAME.$::_armv8_cpu_name.0
316 set _v8_smp_targets ""
318 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
320 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
321 -baseaddr [lindex $ARMV8_CTIBASE $_core]
323 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
324 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
325 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
327 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
329 if { $_v8_smp_debug == 0 } {
330 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
332 # gdb-attach default rule
336 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
338 # gdb-attach default rule
344 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
345 set _armv8_up_cmd "$_armv8_cpu_name"_up
346 # Available if V8_SMP_DEBUG is set to non-zero value
347 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
349 if { $_v8_smp_debug == 0 } {
350 proc $_armv8_up_cmd { args } {
351 foreach _core $args {
357 proc $_armv8_smp_cmd { args } {
361 target smp {*}$_v8_smp_targets
364 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
365 set _r5_name [lindex $R5_NAMES $_core]
366 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
367 -baseaddr [lindex $R5_CTIBASE $_core]
369 # inactive core examination will fail - wait till startup of additional core
370 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
371 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
372 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
374 $_TARGETNAME.$_r5_name configure -event gdb-attach {
376 # gdb-attach default rule
381 proc r5_up { args } {
382 foreach _core $args {
388 if { $_gp_mcu_cores != 0 } {
389 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
390 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
391 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
392 $_TARGETNAME.gp_mcu configure -event reset-assert { }
395 # To access GP MCU, we need to enable the JTAG access for the same.
396 # Ensure Power-AP unlocked
397 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
398 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
400 $::_TARGETNAME.gp_mcu arp_examine
403 $_TARGETNAME.gp_mcu configure -event gdb-attach {
405 # gdb-attach default rule
410 # In case of DMEM access, configure the dmem adapter with offsets from above.
411 if { 0 == [string compare [adapter name] dmem ] } {
412 if { [info exists _dmem_base_address] } {
413 # DAPBUS (Debugger) description
414 dmem base_address $_dmem_base_address
415 dmem ap_address_offset $_dmem_ap_address_offset
416 dmem max_aps $_dmem_max_aps
418 # The following are the details of APs to be emulated for direct address access.
419 # Debug Config (Debugger) description
420 dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
421 dmem emu_ap_list $_dmem_emu_ap_list
422 # We are going local bus, so speed is really dummy here.
425 puts "ERROR: ${SOC} data is missing to support dmem access!"
428 # AXI AP access port for SoC address map
429 target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num