1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
6 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
7 # * J721E: https://www.ti.com/lit/pdf/spruil1
8 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
10 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
11 # * J721S2: https://www.ti.com/lit/pdf/spruj28
12 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
13 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
14 # Has 8 ARMV8 Cores and 8 R5 Cores
15 # * AM642: https://www.ti.com/lit/pdf/spruim2
16 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
17 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
18 # Has 4 ARMV8 Cores and 1 R5 Core and an M4F
19 # * AM62a7: https://www.ti.com/lit/pdf/spruj16a
20 # Has 4 ARMV8 Cores and 2 R5 Cores
21 # * AM62P: https://www.ti.com/lit/pdf/spruj83
22 # Has 4 ARMV8 Cores and 2 R5 Cores
25 source [find target/swj-dp.tcl]
27 if { [info exists SOC] } {
33 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
34 if { [info exists V8_SMP_DEBUG] } {
35 set _v8_smp_debug $V8_SMP_DEBUG
42 # System Controller is the very first processor - all current SoCs have it.
43 set CM3_CTIBASE {0x3C016000}
45 # sysctrl power-ap unlock offsets
46 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
48 # All the ARMV8s are the next processors.
49 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
50 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
51 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
53 # And we add up the R5s
54 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
55 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
56 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
57 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
59 # Finally an General Purpose(GP) MCU
60 set CM4_CTIBASE {0x20001000}
62 # General Purpose MCU (M4) may be present on some very few SoCs
64 # General Purpose MCU power-ap unlock offsets
65 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
67 # Set configuration overrides for each SOC
70 set _K3_DAP_TAPID 0x0bb5a02f
72 # AM654 has 2 clusters of 2 A53 cores each.
73 set _armv8_cpu_name a53
76 # AM654 has 1 cluster of 2 R5s cores.
78 set R5_NAMES {mcu_r5.0 mcu_r5.1}
80 # Sysctrl power-ap unlock offsets
81 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
84 set _K3_DAP_TAPID 0x0bb3802f
86 # AM642 has 1 clusters of 2 A53 cores each.
87 set _armv8_cpu_name a53
89 set ARMV8_DBGBASE {0x90010000 0x90110000}
90 set ARMV8_CTIBASE {0x90020000 0x90120000}
92 # AM642 has 2 cluster of 2 R5s cores.
94 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
95 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
96 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
102 set _K3_DAP_TAPID 0x0bb7e02f
104 # AM625 has 1 clusters of 4 A53 cores.
105 set _armv8_cpu_name a53
107 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
108 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
110 # AM625 has 1 cluster of 1 R5s core.
112 set R5_NAMES {main0_r5.0}
113 set R5_DBGBASE {0x9d410000}
114 set R5_CTIBASE {0x9d418000}
117 set CM3_CTIBASE {0x20001000}
118 # Sysctrl power-ap unlock offsets
119 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
123 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
125 # Setup DMEM access descriptions
126 # DAPBUS (Debugger) description
127 set _dmem_base_address 0x740002000
128 set _dmem_ap_address_offset 0x100
130 # Emulated AP description
131 set _dmem_emu_base_address 0x760000000
132 set _dmem_emu_base_address_map_to 0x1d500000
133 set _dmem_emu_ap_list 1
137 set _K3_DAP_TAPID 0x0bb8d02f
139 # AM62a7/AM62P has 1 cluster of 4 A53 cores.
140 set _armv8_cpu_name a53
142 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
143 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
145 # AM62a7/AM62P has 2 cluster of 1 R5 core.
147 set R5_NAMES {main0_r5.0 mcu0_r5.0}
148 set R5_DBGBASE {0x9d410000 0x9d810000}
149 set R5_CTIBASE {0x9d418000 0x9d818000}
152 set CM3_CTIBASE {0x20001000}
153 # Sysctrl power-ap unlock offsets
154 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
156 # Overrides for am62p
157 if { "$_soc" == "am62p" } {
158 set _K3_DAP_TAPID 0x0bb9d02f
159 set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
163 set _K3_DAP_TAPID 0x0bb6402f
164 # J721E has 1 cluster of 2 A72 cores.
165 set _armv8_cpu_name a72
168 # J721E has 3 clusters of 2 R5 cores each.
171 # Setup DMEM access descriptions
172 # DAPBUS (Debugger) description
173 set _dmem_base_address 0x4c40002000
174 set _dmem_ap_address_offset 0x100
176 # Emulated AP description
177 set _dmem_emu_base_address 0x4c60000000
178 set _dmem_emu_base_address_map_to 0x1d600000
179 set _dmem_emu_ap_list 1
182 set _K3_DAP_TAPID 0x0bb6d02f
184 # J7200 has 1 cluster of 2 A72 cores.
185 set _armv8_cpu_name a72
188 # J7200 has 2 clusters of 2 R5 cores each.
190 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
191 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
194 set CM3_CTIBASE {0x20001000}
197 set _K3_DAP_TAPID 0x0bb7502f
199 # J721s2 has 1 cluster of 2 A72 cores.
200 set _armv8_cpu_name a72
203 # J721s2 has 3 clusters of 2 R5 cores each.
207 set CM3_CTIBASE {0x20001000}
208 # Sysctrl power-ap unlock offsets
209 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
213 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
216 set _K3_DAP_TAPID 0x0bb8002f
218 # j784s4 has 2 cluster of 4 A72 cores each.
219 set _armv8_cpu_name a72
221 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
222 0x90810000 0x90910000 0x90a10000 0x90b10000}
223 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
224 0x90820000 0x90920000 0x90a20000 0x90b20000}
226 # J721s2 has 4 clusters of 2 R5 cores each.
228 set R5_DBGBASE {0x9d010000 0x9d012000
229 0x9d410000 0x9d412000
230 0x9d510000 0x9d512000
231 0x9d610000 0x9d612000}
232 set R5_CTIBASE {0x9d018000 0x9d019000
233 0x9d418000 0x9d419000
234 0x9d518000 0x9d519000
235 0x9d618000 0x9d619000}
236 set R5_NAMES {mcu_r5.0 mcu_r5.1
237 main0_r5.0 main0_r5.1
238 main1_r5.0 main1_r5.1
239 main2_r5.0 main2_r5.1}
242 set CM3_CTIBASE {0x20001000}
243 # Sysctrl power-ap unlock offsets
244 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
247 echo "'$_soc' is invalid!"
253 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
255 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
257 set _TARGETNAME $_CHIPNAME.cpu
259 set _CTINAME $_CHIPNAME.cti
261 # sysctrl is always present
262 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
263 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
264 $_TARGETNAME.sysctrl configure -event reset-assert { }
267 # To access sysctrl, we need to enable the JTAG access for the same.
268 # Ensure Power-AP unlocked
269 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
270 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
272 $::_TARGETNAME.sysctrl arp_examine
275 $_TARGETNAME.sysctrl configure -event gdb-attach {
277 # gdb-attach default rule
281 proc _cpu_no_smp_up {} {
282 set _current_target [target current]
283 set _current_type [$_current_target cget -type]
285 $_current_target arp_examine
286 $_current_target $_current_type dbginit
289 proc _armv8_smp_up {} {
290 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
291 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
292 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
293 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
295 # Set Default target as core 0
296 targets $::_TARGETNAME.$::_armv8_cpu_name.0
299 set _v8_smp_targets ""
301 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
303 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
304 -baseaddr [lindex $ARMV8_CTIBASE $_core]
306 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
307 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
309 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
311 if { $_v8_smp_debug == 0 } {
312 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
314 # gdb-attach default rule
318 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
320 # gdb-attach default rule
326 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
327 set _armv8_up_cmd "$_armv8_cpu_name"_up
328 # Available if V8_SMP_DEBUG is set to non-zero value
329 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
331 if { $_v8_smp_debug == 0 } {
332 proc $_armv8_up_cmd { args } {
333 foreach _core $args {
339 proc $_armv8_smp_cmd { args } {
343 target smp {*}$_v8_smp_targets
346 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
347 set _r5_name [lindex $R5_NAMES $_core]
348 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
349 -baseaddr [lindex $R5_CTIBASE $_core]
351 # inactive core examination will fail - wait till startup of additional core
352 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
353 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
355 $_TARGETNAME.$_r5_name configure -event gdb-attach {
357 # gdb-attach default rule
362 proc r5_up { args } {
363 foreach _core $args {
369 if { $_gp_mcu_cores != 0 } {
370 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
371 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
372 $_TARGETNAME.gp_mcu configure -event reset-assert { }
375 # To access GP MCU, we need to enable the JTAG access for the same.
376 # Ensure Power-AP unlocked
377 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
378 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
380 $::_TARGETNAME.gp_mcu arp_examine
383 $_TARGETNAME.gp_mcu configure -event gdb-attach {
385 # gdb-attach default rule
390 # In case of DMEM access, configure the dmem adapter with offsets from above.
391 if { 0 == [string compare [adapter name] dmem ] } {
392 if { [info exists _dmem_base_address] } {
393 # DAPBUS (Debugger) description
394 dmem base_address $_dmem_base_address
395 dmem ap_address_offset $_dmem_ap_address_offset
396 dmem max_aps $_dmem_max_aps
398 # The following are the details of APs to be emulated for direct address access.
399 # Debug Config (Debugger) description
400 dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
401 dmem emu_ap_list $_dmem_emu_ap_list
402 # We are going local bus, so speed is really dummy here.
405 puts "ERROR: ${SOC} data is missing to support dmem access!"