Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
[openocd.git] / src / target / arm11_dbgtap.c
index 6a5b7ba289da05ed73a5e571d82fb8dd7a91f736..9e8be889c17320309cbb98bab6f3afb72a71d680 100644 (file)
@@ -75,9 +75,9 @@ int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state
  * \param arm11                        Target state variable.
  * \param num_bits             Length of the data field
  * \param out_data             pointer to the data that will be sent out
- *                                             <em>(data is read when it is added to the JTAG queue)</em>
+ *                                             <em > (data is read when it is added to the JTAG queue)</em>
  * \param in_data              pointer to the memory that will receive data that was clocked in
- *                                             <em>(data is written when the JTAG queue is executed)</em>
+ *                                             <em > (data is written when the JTAG queue is executed)</em>
  * \param field                        target data structure that will be initialized
  */
 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
@@ -237,7 +237,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
 
        arm11->last_dscr = dscr;
 
-       *value=dscr;
+       *value = dscr;
 
        return ERROR_OK;
 }
@@ -479,6 +479,10 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32
  *
  *  To disable this code, try "memwrite burst false"
  *
+ *  FIX!!! should we use multiple TAP_IDLE here or not???
+ *
+ *  https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
+ *  https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
  */
 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
 {

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