/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
* *
#endif
#include "arm11.h"
-#include "jtag.h"
-#include "log.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define JTAG_DEBUG(expr ...) DEBUG(expr)
#else
-#define JTAG_DEBUG(expr ...) do {} while(0)
+#define JTAG_DEBUG(expr ...) do {} while (0)
#endif
+/*
+This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
+behavior of the FTDI driver IIRC was to go via RTI.
+
+Conversely there may be other places in this code where the ARM11 code relies
+on the driver to hit through RTI when coming from Update-?R.
+*/
tap_state_t arm11_move_pi_to_si_via_ci[] =
{
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
* \param arm11 Target state variable.
* \param num_bits Length of the data field
* \param out_data pointer to the data that will be sent out
- * <em>(data is read when it is added to the JTAG queue)</em>
+ * <em > (data is read when it is added to the JTAG queue)</em>
* \param in_data pointer to the memory that will receive data that was clocked in
- * <em>(data is written when the JTAG queue is executed)</em>
+ * <em > (data is written when the JTAG queue is executed)</em>
* \param field target data structure that will be initialized
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
{
- field->tap = arm11->jtag_info.tap;
+ field->tap = arm11->target->tap;
field->num_bits = num_bits;
- field->out_mask = NULL;
- field->in_check_mask = NULL;
- field->in_check_value = NULL;
- field->in_handler = NULL;
- field->in_handler_priv = NULL;
-
field->out_value = out_data;
field->in_value = in_data;
}
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
+void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state)
{
jtag_tap_t *tap;
- tap = arm11->jtag_info.tap;
+ tap = arm11->target->tap;
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
{
* arm11_add_debug_SCAN_N().
*
*/
-static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
+static void arm11_in_handler_SCAN_N(uint8_t *in_value)
{
- /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
- u8 v = *in_value & 0x1F;
+ /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */
+ uint8_t v = *in_value & 0x1F;
if (v != 0x10)
{
LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
- return ERROR_FAIL;
+ jtag_set_error(ERROR_FAIL);
}
JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
- return ERROR_OK;
}
/** Select and write to Scan Chain Register (SCREG)
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
+void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state)
{
JTAG_DEBUG("SCREG <= 0x%02x", chain);
scan_field_t field;
- arm11_setup_field(arm11, 5, &chain, NULL, &field);
-
- field.in_handler = arm11_in_handler_SCAN_N;
+ uint8_t tmp[1];
+ arm11_setup_field(arm11, 5, &chain, &tmp, &field);
arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
+
+ jtag_execute_queue_noclear();
+
+ arm11_in_handler_SCAN_N(tmp);
}
/** Write an instruction into the ITR register
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
+void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
* same as CP14 c1
*
* \param arm11 Target state variable.
- * \return DSCR content
+ * \param value DSCR content
+ * \return Error status
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
+int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
- u32 dscr;
+ uint32_t dscr;
scan_field_t chain1_field;
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
- *value=dscr;
+ *value = dscr;
- return retval;
+ return ERROR_OK;
}
/** Write the Debug Status and Control Register (DSCR)
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- jtag_execute_queue();
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
+
+ return ERROR_OK;
}
* \return Debug reason
*
*/
-enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
+enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
{
switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
{
* \param count Number of opcodes to execute
*
*/
-void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
while (1)
{
- u8 flag;
+ uint8_t flag;
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+ CHECK_RETVAL(jtag_execute_queue());
if (flag)
break;
}
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
* \param opcode ARM opcode
*
*/
-void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
+void arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
{
arm11_run_instr_no_data(arm11, &opcode, 1);
}
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
- u32 Data;
- u8 Ready;
- u8 nRetry;
+ uint32_t Data;
+ uint8_t Ready;
+ uint8_t nRetry;
arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
{
Data = *data;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
- jtag_execute_queue();
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
+
+ return ERROR_OK;
}
/** JTAG path for arm11_run_instr_data_to_core_noack
* layer (FT2232) that is long enough to finish execution on
* the core but still shorter than any manually inducible delays.
*
+ * To disable this code, try "memwrite burst false"
+ *
+ * FIX!!! should we use multiple TAP_IDLE here or not???
+ *
+ * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
+ * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
*/
tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
{
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- u8 Readies[count + 1];
- u8 * ReadyPos = Readies;
+ uint8_t Readies[count + 1];
+ uint8_t * ReadyPos = Readies;
while (count--)
{
if (count)
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE));
jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
}
else
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
+ jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
}
}
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ CHECK_RETVAL(jtag_execute_queue());
size_t error_count = 0;
- {size_t i;
- for (i = 0; i < asizeof(Readies); i++)
+ for (size_t i = 0; i < asizeof(Readies); i++)
{
if (Readies[i] != 1)
{
error_count++;
}
- }}
+ }
if (error_count)
LOG_ERROR("Transfer errors " ZU, error_count);
+
+ return ERROR_OK;
}
* \param data Data word to be passed to the core via DTR
*
*/
-void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
- arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
+ return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
scan_field_t chain5_fields[3];
- u32 Data;
- u8 Ready;
- u8 nRetry;
+ uint32_t Data;
+ uint8_t Ready;
+ uint8_t nRetry;
arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
*data++ = Data;
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
* \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
*
*/
-void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
+void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
{
arm11_run_instr_no_data1(arm11, opcode);
* \param data Data word that will be written to r0 before \p opcode is executed
*
*/
-void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
+void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data)
{
/* MRC p14,0,r0,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
* \param count Number of instructions in the list.
*
*/
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
scan_field_t chain7_fields[3];
- u8 nRW;
- u32 DataOut;
- u8 AddressOut;
- u8 Ready;
- u32 DataIn;
- u8 AddressIn;
+ uint8_t nRW;
+ uint32_t DataOut;
+ uint8_t AddressOut;
+ uint8_t Ready;
+ uint32_t DataIn;
+ uint8_t AddressIn;
arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
- {size_t i;
- for (i = 0; i < count + 1; i++)
+ for (size_t i = 0; i < count + 1; i++)
{
if (i < count)
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
}
}
}
- }}
+ }
- {size_t i;
- for (i = 0; i < count; i++)
+ for (size_t i = 0; i < count; i++)
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
- }}
+ }
+
+ return ERROR_OK;
}
/** Clear VCR and all breakpoints and watchpoints via scan chain 7
arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
arm11_sc7_action_t * pos = clear_bw;
- {size_t i;
- for (i = 0; i < asizeof(clear_bw); i++)
+ for (size_t i = 0; i < asizeof(clear_bw); i++)
{
clear_bw[i].write = true;
clear_bw[i].value = 0;
- }}
+ }
- {size_t i;
- for (i = 0; i < arm11->brp; i++)
+ for (size_t i = 0; i < arm11->brp; i++)
(pos++)->address = ARM11_SC7_BCR0 + i;
- }
- {size_t i;
- for (i = 0; i < arm11->wrp; i++)
+
+ for (size_t i = 0; i < arm11->wrp; i++)
(pos++)->address = ARM11_SC7_WCR0 + i;
- }
+
(pos++)->address = ARM11_SC7_VCR;
* \param arm11 Target state variable.
* \param value Value to be written
*/
-void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
+void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
{
arm11_sc7_action_t set_vcr;
* \param result Pointer where to store result
*
*/
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
{
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
arm11_run_instr_data_finish(arm11);
+
+ return ERROR_OK;
}
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