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Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
[openocd.git] / src / target / arm7tdmi.c
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 14646c3c7774aa272cd40f591d7b5a7920b796aa..929ba1d56f7eee448fbc787e93735bf7f39b7a88 100644 (file)
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -5,7 +5,7 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -110,14 +110,14 @@ int arm7tdmi_examine_debug_reason(target_t *target)
                fields[1].out_value = NULL;
                fields[1].in_value = databus;
 
-               if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+               if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
                {
                        return retval;
                }
                arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
                jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -139,9 +139,9 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 }
 
 static int arm7tdmi_num_bits[]={1, 32};
-static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
+static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint)
 {
-       u32 values[2]={breakpoint, flip_u32(out, 32)};
+       uint32_t values[2]={breakpoint, flip_u32(out, 32)};
 
        jtag_add_dr_out(jtag_info->tap,
                        2,
@@ -155,7 +155,7 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int
 }
 
 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
-static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
+static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint)
 {
        jtag_set_end_state(TAP_DRPAUSE);
        arm_jtag_scann(jtag_info, 0x1);
@@ -165,13 +165,13 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *depr
 }
 
 /* clock the target, reading the databus */
-int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
+int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
 {
        int retval = ERROR_OK;
        scan_field_t fields[2];
 
        jtag_set_end_state(TAP_DRPAUSE);
-       if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+       if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
        {
                return retval;
        }
@@ -189,13 +189,13 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 
        jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
-       jtag_add_callback(arm7flip32, (uint8_t *)in);
+       jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 
        jtag_add_runtest(0, jtag_get_end_state());
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -216,9 +216,9 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 
 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
 {
-       u32 readback=le_to_h_u32(tmp);
+       uint32_t readback = le_to_h_u32(tmp);
        if (flip)
-               readback=flip_u32(readback, 32);
+               readback = flip_u32(readback, 32);
        switch (size)
        {
                case 4:
@@ -245,15 +245,16 @@ void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
        }
 }
 
-static int arm7endianness(uint8_t *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
+static int arm7endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
 {
+  uint8_t *in = (uint8_t *)arg;
        arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1);
        return ERROR_OK;
 }
 
 /* clock the target, and read the databus
  * the *in pointer points to a buffer where elements of 'size' bytes
- * are stored in big (be==1) or little (be==0) endianness
+ * are stored in big (be == 1) or little (be == 0) endianness
  */
 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 {
@@ -261,7 +262,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
        scan_field_t fields[2];
 
        jtag_set_end_state(TAP_DRPAUSE);
-       if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+       if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
        {
                return retval;
        }
@@ -279,20 +280,20 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 
        jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
-       jtag_add_callback4(arm7endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
+       jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
 
        jtag_add_runtest(0, jtag_get_end_state());
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
 
                if (in)
                {
-                       LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
+                       LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
                }
                else
                {
@@ -304,7 +305,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
        return ERROR_OK;
 }
 
-void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
+void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 {
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -361,7 +362,7 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
  * The solution is to arrange for a large out/in scan in this loop and
  * and convert data afterwards.
  */
-void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
+void arm7tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
 {
        int i;
        /* get pointers to arch-specific information */
@@ -382,12 +383,12 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
        for (i = 0; i <= 15; i++)
        {
                if (mask & (1 << i))
-                       /* nothing fetched, STM still in EXECUTE (1+i cycle) */
+                       /* nothing fetched, STM still in EXECUTE (1 + i cycle) */
                        arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
        }
 }
 
-void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
+void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
 {
        int i;
        /* get pointers to arch-specific information */
@@ -395,8 +396,8 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
        int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
-       u32 *buf_u32 = buffer;
-       u16 *buf_u16 = buffer;
+       uint32_t *buf_u32 = buffer;
+       uint16_t *buf_u16 = buffer;
        uint8_t *buf_u8 = buffer;
 
        /* STMIA r0-15, [r0] at debug speed
@@ -411,7 +412,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 
        for (i = 0; i <= 15; i++)
        {
-               /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
+               /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
                if (mask & (1 << i))
                {
                        switch (size)
@@ -430,7 +431,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
        }
 }
 
-void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
+void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 {
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -450,14 +451,14 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
        arm7tdmi_clock_data_in(jtag_info, xpsr);
 }
 
-void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
+void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 {
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
-       LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+       LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
        /* MSR1 fetched */
        arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
@@ -500,7 +501,7 @@ void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps
        arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 }
 
-void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
+void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
 {
        int i;
        /* get pointers to arch-specific information */
@@ -521,13 +522,13 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
        for (i = 0; i <= 15; i++)
        {
                if (mask & (1 << i))
-                       /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
+                       /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
                        arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
        }
        arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 }
 
-void arm7tdmi_load_word_regs(target_t *target, u32 mask)
+void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
 {
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -566,7 +567,7 @@ void arm7tdmi_load_byte_reg(target_t *target, int num)
        arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 }
 
-void arm7tdmi_store_word_regs(target_t *target, u32 mask)
+void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
 {
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -605,7 +606,7 @@ void arm7tdmi_store_byte_reg(target_t *target, int num)
        arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 }
 
-void arm7tdmi_write_pc(target_t *target, u32 pc)
+void arm7tdmi_write_pc(target_t *target, uint32_t pc)
 {
        /* get pointers to arch-specific information */
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -723,8 +724,8 @@ int arm7tdmi_examine(struct target_s *target)
        {
                /* get pointers to arch-specific information */
                reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
-               reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
-               if (t==NULL)
+               reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9);
+               if (t == NULL)
                        return ERROR_FAIL;
 
                (*cache_p) = t;
@@ -738,13 +739,13 @@ int arm7tdmi_examine(struct target_s *target)
                }
                target_set_examined(target);
        }
-       if ((retval=embeddedice_setup(target))!=ERROR_OK)
+       if ((retval = embeddedice_setup(target)) != ERROR_OK)
                return retval;
-       if ((retval=arm7_9_setup(target))!=ERROR_OK)
+       if ((retval = arm7_9_setup(target)) != ERROR_OK)
                return retval;
        if (arm7_9->etm_ctx)
        {
-               if ((retval=etm_setup(target))!=ERROR_OK)
+               if ((retval = etm_setup(target)) != ERROR_OK)
                        return retval;
        }
        return ERROR_OK;
@@ -821,7 +822,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
        return ERROR_OK;
 }
 
-int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
+int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp)
 {
        arm7tdmi_common_t *arm7tdmi;
 
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