arm_semihosting: fix two dead assignments

[openocd.git] / src / target / arm_semihosting.c

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 61f1e7801f443b5daa3044f0db491a3bc681c3f1..792474acf0de7eb66a5b3cadce4f20ddaf45f2bf 100644 (file)
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -123,6 +123,22 @@ static int post_result(struct target *target)
                        uint64_t pc = buf_get_u64(arm->core_cache->reg_list[32].value, 0, 64);
                        buf_set_u64(arm->pc->value, 0, 64, pc + 4);
                        arm->pc->dirty = true;
+               }  else if (arm->core_state == ARM_STATE_ARM) {
+                       /* return value in R0 */
+                       buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
+                       arm->core_cache->reg_list[0].dirty = true;
+
+                       uint32_t pc = buf_get_u32(arm->core_cache->reg_list[32].value, 0, 32);
+                       buf_set_u32(arm->pc->value, 0, 32, pc + 4);
+                       arm->pc->dirty = true;
+               } else if (arm->core_state == ARM_STATE_THUMB) {
+                       /* return value in R0 */
+                       buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
+                       arm->core_cache->reg_list[0].dirty = true;
+
+                       uint32_t pc = buf_get_u32(arm->core_cache->reg_list[32].value, 0, 32);
+                       buf_set_u32(arm->pc->value, 0, 32, pc + 2);
+                       arm->pc->dirty = true;
                }
        } else {
                /* resume execution, this will be pc+2 to skip over the
@@ -275,6 +291,16 @@ int arm_semihosting(struct target *target, int *retval)
                if (target->debug_reason != DBG_REASON_BREAKPOINT)
                        return 0;
 
+               /* According to ARM Semihosting for AArch32 and AArch64:
+                * The HLT encodings are new in version 2.0 of the semihosting specification.
+                * Where possible, have semihosting callers continue to use the previously
+                * existing trap instructions to ensure compatibility with legacy semihosting
+                * implementations.
+                * These trap instructions are HLT for A64, SVC on A+R profile A32 or T32,
+                * and BKPT on M profile.
+                * However, it is necessary to change from SVC to HLT instructions to support
+                * AArch32 semihosting properly in a mixed AArch32/AArch64 system. */
+
                if (arm->core_state == ARM_STATE_AARCH64) {
                        uint32_t insn = 0;
                        r = arm->pc;
@@ -284,9 +310,38 @@ int arm_semihosting(struct target *target, int *retval)
                        if (*retval != ERROR_OK)
                                return 1;
 
-                       /* bkpt 0xAB */
+                       /* HLT 0xF000 */
                        if (insn != 0xD45E0000)
                                return 0;
+               } else if (arm->core_state == ARM_STATE_ARM) {
+                       r = arm->pc;
+                       pc = buf_get_u32(r->value, 0, 32);
+
+                       /* A32 instruction => check for HLT 0xF000 (0xE10F0070) */
+                       uint32_t insn = 0;
+
+                       *retval = target_read_u32(target, pc, &insn);
+
+                       if (*retval != ERROR_OK)
+                               return 1;
+
+                       /* HLT 0xF000*/
+                       if (insn != 0xE10F0070)
+                               return 0;
+               } else if (arm->core_state == ARM_STATE_THUMB) {
+                       r = arm->pc;
+                       pc = buf_get_u32(r->value, 0, 32);
+
+                       /* T32 instruction => check for HLT 0x3C (0xBABC) */
+                       uint16_t insn = 0;
+                       *retval = target_read_u16(target, pc, &insn);
+
+                       if (*retval != ERROR_OK)
+                               return 1;
+
+                       /* HLT 0x3C*/
+                       if (insn != 0xBABC)
+                               return 0;
                } else
                        return 1;
        } else {
@@ -312,10 +367,10 @@ int arm_semihosting(struct target *target, int *retval)
                }
 
                /* Check for ARM operation numbers. */
-               if (0 <= semihosting->op && semihosting->op <= 0x31) {
+               if (semihosting->op >= 0 && semihosting->op <= 0x31) {
                        *retval = semihosting_common(target);
                        if (*retval != ERROR_OK) {
-                               LOG_ERROR("Failed semihosting operation");
+                               LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op);
                                return 0;
                        }
                } else {