}
if (cortex_m->dcb_dhcsr & S_RESET_ST) {
- /* check if still in reset */
- retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
- if (retval != ERROR_OK)
- return retval;
-
- if (cortex_m->dcb_dhcsr & S_RESET_ST) {
- target->state = TARGET_RESET;
- return ERROR_OK;
- }
+ target->state = TARGET_RESET;
+ return ERROR_OK;
}
if (target->state == TARGET_RESET) {
*/
LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
cortex_m->dcb_dhcsr);
- cortex_m_endreset_event(target);
+ retval = cortex_m_endreset_event(target);
+ if (retval != ERROR_OK) {
+ target->state = TARGET_UNKNOWN;
+ return retval;
+ }
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
}
"handler to reset any peripherals or configure hardware srst support.");
}
+ /*
+ SAM4L needs to execute security initalization
+ startup sequence before AP access would be enabled.
+ During the intialization CDBGPWRUPACK is pulled low and we
+ need to wait for it to be set to 1 again.
+ */
+ retval = dap_dp_poll_register(swjdp, DP_CTRL_STAT,
+ CDBGPWRUPACK, CDBGPWRUPACK, 100);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed waitnig for CDBGPWRUPACK");
+ return ERROR_FAIL;
+ }
+
{
/* I do not know why this is necessary, but it
* fixes strange effects (step/resume cause NMI
free(cm->dwt_comparator_list);
goto fail0;
}
- cache->name = "cortex-m3 dwt registers";
+ cache->name = "Cortex-M DWT registers";
cache->num_regs = 2 + cm->dwt_num_comp * 3;
cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
if (!cache->reg_list) {
uint32_t i;
for (i = 0; i < (size * 4); i++) {
- cortex_m_dcc_read(target, &data, &ctrl);
+ int retval = cortex_m_dcc_read(target, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
buffer[i] = data;
}
if (target->state == TARGET_RUNNING) {
uint8_t data;
uint8_t ctrl;
+ int retval;
- cortex_m_dcc_read(target, &data, &ctrl);
+ retval = cortex_m_dcc_read(target, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
/* check if we have data */
if (ctrl & (1 << 0)) {
/* we assume target is quick enough */
request = data;
- cortex_m_dcc_read(target, &data, &ctrl);
- request |= (data << 8);
- cortex_m_dcc_read(target, &data, &ctrl);
- request |= (data << 16);
- cortex_m_dcc_read(target, &data, &ctrl);
- request |= (data << 24);
+ for (int i = 1; i <= 3; i++) {
+ retval = cortex_m_dcc_read(target, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
+ request |= ((uint32_t)data << (i * 8));
+ }
target_request(target, request);
}
}