target/xtensa: avoid IHI for writes to non-executable memory

[openocd.git] / src / target / riscv / riscv_semihosting.c

diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c
index b347212d3417f9e2fd336788f2b0c17ced310a86..da237ef337525ea7a4080a4bed2bbbaf95a43f6d 100644 (file)
--- a/src/target/riscv/riscv_semihosting.c
+++ b/src/target/riscv/riscv_semihosting.c
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
+// SPDX-License-Identifier: GPL-2.0-or-later
 
 /***************************************************************************
  *   Copyright (C) 2018 by Liviu Ionescu                                   *
@@ -12,19 +12,6 @@
  *                                                                         *
  *   Copyright (C) 2016 by Square, Inc.                                    *
  *   Steven Stallion <stallion@squareup.com>                               *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 /**
@@ -44,7 +31,6 @@
 #include <helper/log.h>
 
 #include "target/target.h"
-#include "target/semihosting_common.h"
 #include "riscv.h"
 
 static int riscv_semihosting_setup(struct target *target, int enable);
@@ -67,23 +53,23 @@ void riscv_semihosting_init(struct target *target)
  * @param retval Pointer to a location where the return code will be stored
  * @return non-zero value if a request was processed or an error encountered
  */
-semihosting_result_t riscv_semihosting(struct target *target, int *retval)
+enum semihosting_result riscv_semihosting(struct target *target, int *retval)
 {
        struct semihosting *semihosting = target->semihosting;
        if (!semihosting) {
                LOG_DEBUG("   -> NONE (!semihosting)");
-               return SEMI_NONE;
+               return SEMIHOSTING_NONE;
        }
 
        if (!semihosting->is_active) {
                LOG_DEBUG("   -> NONE (!semihosting->is_active)");
-               return SEMI_NONE;
+               return SEMIHOSTING_NONE;
        }
 
        riscv_reg_t pc;
        int result = riscv_get_register(target, &pc, GDB_REGNO_PC);
        if (result != ERROR_OK)
-               return SEMI_ERROR;
+               return SEMIHOSTING_ERROR;
 
        uint8_t tmp_buf[12];
 
@@ -92,7 +78,7 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval)
                /* Instruction memories may not support arbitrary read size. Use any size that will work. */
                *retval = riscv_read_by_any_size(target, (pc - 4) + 4 * i, 4, tmp_buf + 4 * i);
                if (*retval != ERROR_OK)
-                       return SEMI_ERROR;
+                       return SEMIHOSTING_ERROR;
        }
 
        /*
@@ -111,7 +97,7 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval)
        if (pre != 0x01f01013 || ebreak != 0x00100073 || post != 0x40705013) {
                /* Not the magic sequence defining semihosting. */
                LOG_DEBUG("   -> NONE (no magic)");
-               return SEMI_NONE;
+               return SEMIHOSTING_NONE;
        }
 
        /*
@@ -126,13 +112,13 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval)
                result = riscv_get_register(target, &r0, GDB_REGNO_A0);
                if (result != ERROR_OK) {
                        LOG_DEBUG("   -> ERROR (couldn't read a0)");
-                       return SEMI_ERROR;
+                       return SEMIHOSTING_ERROR;
                }
 
                result = riscv_get_register(target, &r1, GDB_REGNO_A1);
                if (result != ERROR_OK) {
                        LOG_DEBUG("   -> ERROR (couldn't read a1)");
-                       return SEMI_ERROR;
+                       return SEMIHOSTING_ERROR;
                }
 
                semihosting->op = r0;
@@ -140,35 +126,37 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval)
                semihosting->word_size_bytes = riscv_xlen(target) / 8;
 
                /* Check for ARM operation numbers. */
-               if (semihosting->op >= 0 && semihosting->op <= 0x31) {
+               if ((semihosting->op >= 0 && semihosting->op <= 0x31) ||
+                       (semihosting->op >= 0x100 && semihosting->op <= 0x107)) {
+
                        *retval = semihosting_common(target);
                        if (*retval != ERROR_OK) {
                                LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op);
-                               return SEMI_ERROR;
+                               return SEMIHOSTING_ERROR;
                        }
                } else {
                        /* Unknown operation number, not a semihosting call. */
                        LOG_DEBUG("   -> NONE (unknown operation number)");
-                       return SEMI_NONE;
+                       return SEMIHOSTING_NONE;
                }
        }
 
+       /* Resume right after the EBREAK 4 bytes instruction. */
+       *retval = riscv_set_register(target, GDB_REGNO_PC, pc + 4);
+       if (*retval != ERROR_OK)
+               return SEMIHOSTING_ERROR;
+
        /*
         * Resume target if we are not waiting on a fileio
         * operation to complete.
         */
        if (semihosting->is_resumable && !semihosting->hit_fileio) {
-               /* Resume right after the EBREAK 4 bytes instruction. */
-               *retval = riscv_set_register(target, GDB_REGNO_PC, pc + 4);
-               if (*retval != ERROR_OK)
-                       return SEMI_ERROR;
-
                LOG_DEBUG("   -> HANDLED");
-               return SEMI_HANDLED;
+               return SEMIHOSTING_HANDLED;
        }
 
        LOG_DEBUG("   -> WAITING");
-       return SEMI_WAITING;
+       return SEMIHOSTING_WAITING;
 }
 
 /* -------------------------------------------------------------------------