Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into

[openocd.git] / src / target / xscale.c

diff --git a/src/target/xscale.c b/src/target/xscale.c
index e87f5527a4de179c74b5d531e0f0dea9cb6f3a5b..40126c92837cf746382be1ac4551eef5c1e21956 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2,9 +2,12 @@
  *   Copyright (C) 2006, 2007 by Dominic Rath                              *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
+ *   Copyright (C) 2009 Michael Schwingen                                  *
+ *   michael@schwingen.org                                                 *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -959,7 +962,7 @@ int xscale_arch_state(struct target_s *target)
                        "MMU: %s, D-Cache: %s, I-Cache: %s"
                        "%s",
                         armv4_5_state_strings[armv4_5->core_state],
-                        Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
+                        Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
                         armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
                         buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
                         buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
@@ -1202,7 +1205,7 @@ int xscale_halt(target_t *target)
        xscale_common_t *xscale = armv4_5->arch_info;
 
        LOG_DEBUG("target->state: %s",
-                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+                 target_state_name(target));
 
        if (target->state == TARGET_HALTED)
        {
@@ -1568,7 +1571,7 @@ int xscale_assert_reset(target_t *target)
        xscale_common_t *xscale = armv4_5->arch_info;
 
        LOG_DEBUG("target->state: %s",
-                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+                 target_state_name(target));
 
        /* select DCSR instruction (set endstate to R-T-I to ensure we don't
         * end up in T-L-R, which would reset JTAG
@@ -3384,6 +3387,65 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch
 }
 
 
+int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+{
+       target_t *target = get_current_target(cmd_ctx);
+       armv4_5_common_t *armv4_5;
+       xscale_common_t *xscale;
+       int err = 0;
+
+       if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
+       {
+               return ERROR_OK;
+       }
+
+       if (argc == 0) /* print current settings */
+       {
+               int idx;
+
+               command_print(cmd_ctx, "active user-set static vectors:");
+               for (idx = 1; idx < 8; idx++)
+                       if (xscale->static_low_vectors_set & (1 << idx))
+                               command_print(cmd_ctx, "low  %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
+               for (idx = 1; idx < 8; idx++)
+                       if (xscale->static_high_vectors_set & (1 << idx))
+                               command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
+               return ERROR_OK;
+       }
+
+       if (argc != 3)
+               err = 1;
+       else
+       {
+               int idx;
+               uint32_t vec;
+               idx = strtoul(args[1], NULL, 0);
+               vec = strtoul(args[2], NULL, 0);
+
+               if (idx < 1 || idx >= 8)
+                       err = 1;
+
+               if (!err && strcmp(args[0], "low") == 0)
+               {
+                       xscale->static_low_vectors_set |= (1<<idx);
+                       xscale->static_low_vectors[idx] = vec;
+               }
+               else if (!err && (strcmp(args[0], "high") == 0))
+               {
+                       xscale->static_high_vectors_set |= (1<<idx);
+                       xscale->static_high_vectors[idx] = vec;
+               }
+               else
+                       err = 1;
+       }
+
+       if (err)
+               command_print(cmd_ctx, "usage: xscale vector_table <high|low> <index> <code>");
+
+       return ERROR_OK;
+}
+
+
 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
        target_t *target = get_current_target(cmd_ctx);
@@ -3692,6 +3754,7 @@ int xscale_register_commands(struct command_context_s *cmd_ctx)
        register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
 
        register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
+       register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
 
        register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");