cfg: add srst_nogate to the supported targets, remove from board configs

[openocd.git] / tcl / target / stm32f1x.cfg

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index f32654a57abf41ac27e3dc225ac2a4353836784d..6a62992d263097b551284533b8ab280e4a8ecec0 100644 (file)
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -11,11 +11,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f1x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 4kB (as found on some STM32F100s)
@@ -29,9 +25,13 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # See STM Document RM0008
-  # Section 26.6.3
-   set _CPUTAPID 0x3ba00477
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -61,8 +61,8 @@ if { [info exists BSTAPID] } {
   set _BSTAPID9 0x06428041
 }
 
-if {$using_jtag} {
- jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
        -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
        -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
        -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
@@ -82,10 +82,14 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-if {$using_jtag} {
+if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}