--- /dev/null
+#Written by: Michael Schwingen <rincewind@discworld.dascon.de>\r
+#############################################################################\r
+# setup expansion bus CS, disable external wdt\r
+#############################################################################\r
+mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000\r
+mww 0xc4000004 0x94d10013 #CS1\r
+mww 0xc4000008 0x95960003 #CS2\r
+mww 0xc400000c 0x00000000 #CS3\r
+mww 0xc4000010 0x80900003 #CS4\r
+mww 0xc4000014 0x9d520003 #CS5\r
+mww 0xc4000018 0x81860001 #CS6\r
+mww 0xc400001c 0x80900003 #CS7\r
+\r
+#############################################################################\r
+# init SDRAM controller: 16MB, one bank, CL3\r
+#############################################################################\r
+mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3\r
+mww 0xCC000004 0 # disable refresh\r
+mww 0xCC000008 3 # NOP\r
+sleep 100\r
+mww 0xCC000004 2100 # set refresh counter\r
+mww 0xCC000008 2 # Precharge All Banks\r
+sleep 100\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 4 # Auto Refresh\r
+mww 0xCC000008 1 # Mode Select CL3\r
+\r
+#mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash\r
+#mirror at 0x00000000\r
+\r
+#\r
+# detect flash\r
+#\r
+flash probe 0\r
--- /dev/null
+#Written by: Michael Schwingen <rincewind@discworld.dascon.de>\r
+\r
+reset_config trst_and_srst separate\r
+\r
+jtag_nsrst_delay 100\r
+jtag_ntrst_delay 100\r
+\r
+#jtag scan chain\r
+#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE)\r
+jtag_device 7 0x1 0x7f 0x7e\r
+\r
+daemon_startup reset\r
+\r
+#target <type> <endianess> <reset mode> <JTAG pos> <variant>\r
+target xscale big reset_init 0 ixp42x\r
+#target xscale big run_and_halt 0 ixp42x\r
+target_script 0 reset event/xba_revA3.script\r
+\r
+run_and_halt_time 0 100\r
+\r
+flash bank cfi 0x50000000 0x400000 2 2 0\r
+working_area 0 0x20010000 0x8000 nobackup\r
+\r
+# halt target\r
+wait_halt\r
+\r
+# set big endian mode\r
+reg XSCALE_CTRL 0xF8\r