openocd: remove CamelCase symbols *xPSR*

We have left the camelcase symbols *xPSR* for some time, to avoid
any conflict with possibly pending patches in gerrit.
With the approaching v0.12.0-rc1, it's time to revisit it.
The patches in gerrit that conflict with this rename are all not
merge-able due to conflicts or due to negative review.

Drop these CamelCase symbols.

Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7155
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c
index 3afad3d029f55f8cd8d1a51e3852381ed29d07be..6b20ed322342c732d70af03982dee39cc8f88b5a 100644 (file)
--- a/src/rtos/nuttx.c
+++ b/src/rtos/nuttx.c
@@ -103,7 +103,7 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = {
        { ARMV7M_R13,     0,  32 },             /* sp   */
        { ARMV7M_R14,   0x3c, 32 },             /* lr   */
        { ARMV7M_PC,    0x40, 32 },             /* pc   */
-       { ARMV7M_xPSR,  0x44, 32 },             /* xPSR */
+       { ARMV7M_XPSR,  0x44, 32 },             /* xPSR */
 };
 
 
@@ -131,7 +131,7 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
        { ARMV7M_R13,     0,  32 },             /* sp   */
        { ARMV7M_R14,   0x80, 32 },             /* lr   */
        { ARMV7M_PC,    0x84, 32 },             /* pc   */
-       { ARMV7M_xPSR,  0x88, 32 },             /* xPSR */
+       { ARMV7M_XPSR,  0x88, 32 },             /* xPSR */
 };
 
 static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {

diff --git a/src/rtos/rtos_chibios_stackings.c b/src/rtos/rtos_chibios_stackings.c
index bd17171612c2ddb83f0e3f0d88e367fec20f9059..38a2889bd94b69a3d5b826f09d6a73b95c6f0a85 100644 (file)
--- a/src/rtos/rtos_chibios_stackings.c
+++ b/src/rtos/rtos_chibios_stackings.c
@@ -32,7 +32,7 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARM
        { ARMV7M_R13,  -2,   32 },              /* sp   */
        { ARMV7M_R14,  -1,   32 },              /* lr   */
        { ARMV7M_PC,   0x20, 32 },              /* pc   */
-       { ARMV7M_xPSR, -1,   32 },              /* xPSR */
+       { ARMV7M_XPSR, -1,   32 },              /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
@@ -59,7 +59,7 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_f
        { ARMV7M_R13,  -2,   32 },              /* sp   */
        { ARMV7M_R14,  -1,   32 },              /* lr   */
        { ARMV7M_PC,   0x60, 32 },              /* pc   */
-       { ARMV7M_xPSR, -1,   32 },              /* xPSR */
+       { ARMV7M_XPSR, -1,   32 },              /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {

diff --git a/src/rtos/rtos_ecos_stackings.c b/src/rtos/rtos_ecos_stackings.c
index f5c08fe7366d114105a08936c42499703bdd66d7..b15915046f6f2fcfa2525d6def02ceddaaeab307 100644 (file)
--- a/src/rtos/rtos_ecos_stackings.c
+++ b/src/rtos/rtos_ecos_stackings.c
@@ -25,7 +25,7 @@ static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV
        { ARMV7M_R13,  -2,   32 },              /* sp   */
        { ARMV7M_R14,  -1,   32 },              /* lr   */
        { ARMV7M_PC,   0x40, 32 },              /* pc   */
-       { ARMV7M_xPSR, -1,   32 },              /* xPSR */
+       { ARMV7M_XPSR, -1,   32 },              /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = {

diff --git a/src/rtos/rtos_embkernel_stackings.c b/src/rtos/rtos_embkernel_stackings.c
index 46e13bc2fc9638a5b894212c676922d698eb06af..bf02cb79927c365d1afbeb8304091019fd03fe50 100644 (file)
--- a/src/rtos/rtos_embkernel_stackings.c
+++ b/src/rtos/rtos_embkernel_stackings.c
@@ -30,7 +30,7 @@ static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[
        { ARMV7M_R13,  -2,   32 },          /* sp   */
        { ARMV7M_R14,  0x38, 32 },              /* lr   */
        { ARMV7M_PC,   0x3c, 32 },              /* pc   */
-       { ARMV7M_xPSR, 0x40, 32 },              /* xPSR */
+       { ARMV7M_XPSR, 0x40, 32 },              /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = {

diff --git a/src/rtos/rtos_mqx_stackings.c b/src/rtos/rtos_mqx_stackings.c
index 90a2e0161aec312ca3c6eabe50b0622941b74cb3..087591baaa6d254a7b44bd1af132a7d37b8c8c50 100644 (file)
--- a/src/rtos/rtos_mqx_stackings.c
+++ b/src/rtos/rtos_mqx_stackings.c
@@ -56,7 +56,7 @@ static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_
        { ARMV7M_R13,    -2, 32 }, /* sp   */
        { ARMV7M_R14,  0x28, 32 }, /* lr   */
        { ARMV7M_PC,   0x44, 32 }, /* pc   */
-       { ARMV7M_xPSR, 0x48, 32 }, /* xPSR */
+       { ARMV7M_XPSR, 0x48, 32 }, /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = {

diff --git a/src/rtos/rtos_riot_stackings.c b/src/rtos/rtos_riot_stackings.c
index 30eecd6b7784713e06a2a524673e63a1b711e220..bcf14e54fb68adae8584f5d7005589c040202c97 100644 (file)
--- a/src/rtos/rtos_riot_stackings.c
+++ b/src/rtos/rtos_riot_stackings.c
@@ -43,7 +43,7 @@ static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV
        { ARMV7M_R13,   -2,   32 },             /* sp   */
        { ARMV7M_R14,   0x38, 32 },             /* lr   */
        { ARMV7M_PC,    0x3c, 32 },             /* pc   */
-       { ARMV7M_xPSR,  0x40, 32 },             /* xPSR */
+       { ARMV7M_XPSR,  0x40, 32 },             /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
@@ -72,7 +72,7 @@ static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARM
        { ARMV7M_R13,   -2,   32 },     /* sp   */
        { ARMV7M_R14,   0x38, 32 },     /* lr   */
        { ARMV7M_PC,    0x3c, 32 },     /* pc   */
-       { ARMV7M_xPSR,  0x40, 32 },     /* xPSR */
+       { ARMV7M_XPSR,  0x40, 32 },     /* xPSR */
 };
 
 const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {

diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
index ebdc64c2a0d5bfc55d53be4eedbdce9e19ea95ac..059bfc5b401434614b33b7060239b60ffbddb7e5 100644 (file)
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -29,7 +29,7 @@ static const struct stack_register_offset rtos_standard_cortex_m3_stack_offsets[
        { ARMV7M_R13,  -2,   32 },              /* sp   */
        { ARMV7M_R14,  0x34, 32 },              /* lr   */
        { ARMV7M_PC,   0x38, 32 },              /* pc   */
-       { ARMV7M_xPSR, 0x3c, 32 },              /* xPSR */
+       { ARMV7M_XPSR, 0x3c, 32 },              /* xPSR */
 };
 
 static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets[] = {
@@ -49,7 +49,7 @@ static const struct stack_register_offset rtos_standard_cortex_m4f_stack_offsets
        { ARMV7M_R13,  -2,   32 },              /* sp   */
        { ARMV7M_R14,  0x38, 32 },              /* lr   */
        { ARMV7M_PC,   0x3c, 32 },              /* pc   */
-       { ARMV7M_xPSR, 0x40, 32 },              /* xPSR */
+       { ARMV7M_XPSR, 0x40, 32 },              /* xPSR */
 };
 
 static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_offsets[] = {
@@ -69,7 +69,7 @@ static const struct stack_register_offset rtos_standard_cortex_m4f_fpu_stack_off
        { ARMV7M_R13,  -2,   32 },              /* sp   */
        { ARMV7M_R14,  0x78, 32 },              /* lr   */
        { ARMV7M_PC,   0x7c, 32 },              /* pc   */
-       { ARMV7M_xPSR, 0x80, 32 },              /* xPSR */
+       { ARMV7M_XPSR, 0x80, 32 },              /* xPSR */
 };
 
 

diff --git a/src/rtos/rtos_ucos_iii_stackings.c b/src/rtos/rtos_ucos_iii_stackings.c
index 8662518209f8b7735ae7fc31ec7e32f98bd8d3d0..aa98cc7a94d4ef42c286396442d49b1d71b3a65b 100644 (file)
--- a/src/rtos/rtos_ucos_iii_stackings.c
+++ b/src/rtos/rtos_ucos_iii_stackings.c
@@ -32,7 +32,7 @@ static const struct stack_register_offset rtos_ucos_iii_cortex_m_stack_offsets[]
        { ARMV7M_R13,  -2,   32 },      /* sp   */
        { ARMV7M_R14,  0x34, 32 },      /* lr   */
        { ARMV7M_PC,   0x38, 32 },      /* pc   */
-       { ARMV7M_xPSR, 0x3c, 32 },      /* xPSR */
+       { ARMV7M_XPSR, 0x3c, 32 },      /* xPSR */
 };
 
 static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[] = {

diff --git a/src/rtos/zephyr.c b/src/rtos/zephyr.c
index 6276236e2956bea5680af4f702526a4d833c4f51..5f7795337191f982eba51abb16f691946c24c501 100644 (file)
--- a/src/rtos/zephyr.c
+++ b/src/rtos/zephyr.c
@@ -136,7 +136,7 @@ static const struct stack_register_offset arm_cpu_saved[] = {
        { ARMV7M_R13,  -2, 32 },
        { ARMV7M_R14,  20, 32 },
        { ARMV7M_PC,   24, 32 },
-       { ARMV7M_xPSR, 28, 32 },
+       { ARMV7M_XPSR, 28, 32 },
 };
 
 static struct stack_register_offset arc_cpu_saved[] = {

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index be0de509b79d10cc5cbe52a30b15877ce4f6dd94..5d67d51f48e4201b2a831cf56d37f28d1c7bc433 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -53,7 +53,7 @@ const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
        ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
        ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
        ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
-       ARMV7M_xPSR,
+       ARMV7M_XPSR,
 };
 
 /* MSP is used in handler and some thread modes */
@@ -62,7 +62,7 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
        ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
        ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
        ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
-       ARMV7M_xPSR,
+       ARMV7M_XPSR,
 };
 
 /*
@@ -97,7 +97,7 @@ static const struct {
        { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
        { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
        { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
-       { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+       { ARMV7M_XPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
 
        { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
        { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
@@ -245,7 +245,7 @@ uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id)
        switch (arm_reg_id) {
        case ARMV7M_R0 ... ARMV7M_R14:
        case ARMV7M_PC:
-       case ARMV7M_xPSR:
+       case ARMV7M_XPSR:
        case ARMV7M_MSP:
        case ARMV7M_PSP:
                /* NOTE:  we "know" here that the register identifiers
@@ -579,7 +579,7 @@ int armv7m_start_algorithm(struct target *target,
                 * Because xPSR.T is populated on reset from the vector table,
                 * it might be 0 if the vector table has "bad" data in it.
                 */
-               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+               struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_XPSR];
                buf_set_u32(reg->value, 0, 32, 0x01000000);
                reg->valid = true;
                reg->dirty = true;
@@ -803,7 +803,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
                        LOG_ERROR("unable to allocate reg type list");
        }
 
-       arm->cpsr = reg_list + ARMV7M_xPSR;
+       arm->cpsr = reg_list + ARMV7M_XPSR;
        arm->pc = reg_list + ARMV7M_PC;
        arm->core_cache = cache;
 

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9ac6b9ec9dc2fe6aa1d294e937a4764ac679d16f..188bd5652eb502a8828d4169ee1aac8e84089a02 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -46,7 +46,7 @@ enum {
        ARMV7M_REGSEL_R14,
        ARMV7M_REGSEL_PC = 15,
 
-       ARMV7M_REGSEL_xPSR = 16,
+       ARMV7M_REGSEL_XPSR = 16,
        ARMV7M_REGSEL_MSP,
        ARMV7M_REGSEL_PSP,
 
@@ -124,7 +124,7 @@ enum {
        ARMV7M_R14 = ARMV7M_REGSEL_R14,
        ARMV7M_PC = ARMV7M_REGSEL_PC,
 
-       ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
+       ARMV7M_XPSR = ARMV7M_REGSEL_XPSR,
        ARMV7M_MSP = ARMV7M_REGSEL_MSP,
        ARMV7M_PSP = ARMV7M_REGSEL_PSP,
 
@@ -199,7 +199,7 @@ enum {
        /* for convenience add registers' block delimiters */
        ARMV7M_LAST_REG,
        ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
-       ARMV7M_CORE_LAST_REG = ARMV7M_xPSR,
+       ARMV7M_CORE_LAST_REG = ARMV7M_XPSR,
        ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
        ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
        ARMV8M_FIRST_REG = ARMV8M_MSP_NS,

diff --git a/src/target/armv8.c b/src/target/armv8.c
index f4ae1f55cf933479318812a650e0bd7e140757d1..0da6c05a5e4efe06bce64266eb581852649c7891 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -134,7 +134,7 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
                retval = dpm->instr_read_data_r0_64(dpm,
                                ARMV8_MRS_DLR(0), &value_64);
                break;
-       case ARMV8_xPSR:
+       case ARMV8_XPSR:
                retval = dpm->instr_read_data_r0(dpm,
                                ARMV8_MRS_DSPSR(0), &value);
                value_64 = value;
@@ -249,7 +249,7 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
                        ARMV8_MSR_DLR(0),
                        value_64);
                break;
-       case ARMV8_xPSR:
+       case ARMV8_XPSR:
                value = value_64;
                retval = dpm->instr_write_data_r0(dpm,
                        ARMV8_MSR_DSPSR(0),
@@ -364,7 +364,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
                        ARMV8_MRC_DLR(0),
                        &value);
                break;
-       case ARMV8_xPSR:
+       case ARMV8_XPSR:
                retval = dpm->instr_read_data_r0(dpm,
                        ARMV8_MRC_DSPSR(0),
                        &value);
@@ -399,17 +399,17 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
                break;
        case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
                retval = dpm->instr_read_data_r0(dpm,
-                               ARMV8_MRS_xPSR_T1(1, 0),
+                               ARMV8_MRS_XPSR_T1(1, 0),
                                &value);
                break;
        case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
                retval = dpm->instr_read_data_r0(dpm,
-                               ARMV8_MRS_xPSR_T1(1, 0),
+                               ARMV8_MRS_XPSR_T1(1, 0),
                                &value);
                break;
        case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
                retval = dpm->instr_read_data_r0(dpm,
-                               ARMV8_MRS_xPSR_T1(1, 0),
+                               ARMV8_MRS_XPSR_T1(1, 0),
                                &value);
                break;
        case ARMV8_FPSR:
@@ -500,7 +500,7 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
                retval = dpm->instr_write_data_r0(dpm,
                                ARMV8_MCR_DLR(0), value);
                break;
-       case ARMV8_xPSR: /* CPSR */
+       case ARMV8_XPSR: /* CPSR */
                /* read r0 from DCC, then "MCR r0, DSPSR" */
                retval = dpm->instr_write_data_r0(dpm,
                                ARMV8_MCR_DSPSR(0), value);
@@ -535,17 +535,17 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
                break;
        case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
                retval = dpm->instr_write_data_r0(dpm,
-                               ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+                               ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
                                value);
                break;
        case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
                retval = dpm->instr_write_data_r0(dpm,
-                               ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+                               ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
                                value);
                break;
        case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
                retval = dpm->instr_write_data_r0(dpm,
-                               ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+                               ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
                                value);
                break;
        case ARMV8_FPSR:
@@ -1364,7 +1364,7 @@ static const struct {
 
        { ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
        { ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
-       { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
+       { ARMV8_XPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
                "general", "org.gnu.gdb.aarch64.core", aarch64_flags_cpsr},
        { ARMV8_V0,  "v0",  128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
        { ARMV8_V1,  "v1",  128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
@@ -1449,7 +1449,7 @@ static const struct {
        { ARMV8_R13, 0, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
        { ARMV8_R14, 0, "lr",  32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
        { ARMV8_PC, 0, "pc",   32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
-       { ARMV8_xPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+       { ARMV8_XPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
        { ARMV8_V0, 0, "d0",  64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
        { ARMV8_V0, 8, "d1",  64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
        { ARMV8_V1, 0, "d2",  64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
@@ -1652,7 +1652,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
                        LOG_ERROR("unable to allocate reg type list");
        }
 
-       arm->cpsr = reg_list + ARMV8_xPSR;
+       arm->cpsr = reg_list + ARMV8_XPSR;
        arm->pc = reg_list + ARMV8_PC;
        arm->core_cache = cache;
 

diff --git a/src/target/armv8.h b/src/target/armv8.h
index e06067175bb044758873f54ee8c55c4444417dc4..2ed3a65acd9e8fb3f015f99b690a71090d3a9d2a 100644 (file)
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -49,7 +49,7 @@ enum {
 
        ARMV8_SP = 31,
        ARMV8_PC = 32,
-       ARMV8_xPSR = 33,
+       ARMV8_XPSR = 33,
 
        ARMV8_V0 = 34,
        ARMV8_V1,

diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 017c175fcdbde8f355905050f6944043e5299381..3ea8fa9640ae84327cd6802a01093d1e8432806c 100644 (file)
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -601,7 +601,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
                                /* load SPSR with the desired mode and execute DRPS */
                                LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
                                retval = dpm->instr_write_data_r0(dpm,
-                                               ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);
+                                               ARMV8_MSR_GP_XPSR_T1(1, 0, 15), cpsr);
                                if (retval == ERROR_OK)
                                        retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
                        }
@@ -917,7 +917,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                if (!cache->reg_list[i].exist)
                        continue;
                /* skip PC and CPSR */
-               if (i == ARMV8_PC || i == ARMV8_xPSR)
+               if (i == ARMV8_PC || i == ARMV8_XPSR)
                        continue;
                /* skip invalid */
                if (!cache->reg_list[i].valid)
@@ -939,7 +939,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
        /* flush CPSR and PC */
        if (retval == ERROR_OK)
-               retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR);
+               retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_XPSR], ARMV8_XPSR);
        if (retval == ERROR_OK)
                retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
        /* flush R0 -- it's *very* dirty by now */
@@ -1293,9 +1293,9 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
        unsigned int el;
 
        static const int clobbered_regs_by_el[3][5] = {
-               { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
-               { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
-               { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
+               { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
+               { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
+               { ARMV8_PC, ARMV8_XPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
        };
 
        el = (dpm->dscr >> 8) & 3;
@@ -1310,7 +1310,7 @@ void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
        mem_ap_write_u32(armv8->debug_ap,
                armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
 
-       armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
+       armv8->read_reg_u64(armv8, ARMV8_XPSR, &dlr);
        dspsr = dlr;
        armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);
 

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index c4ecd667c034392334b97d09443588576bd729ad..8c9652bfedd94b07dcede37988463e21922f8ed5 100644 (file)
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -138,9 +138,9 @@
        (0xd500401f | ((op1) << 16)  | ((crm) << 8) | ((op2) << 5))
 
 #define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
-#define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
+#define ARMV8_MRS_XPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
 #define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
-#define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
+#define ARMV8_MSR_GP_XPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
 
 #define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
 #define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index c5cb8d47abd1a8a0cc6df5cd4098c5e40da52d94..2e81d140cf95868c7653b9ef4645815cd1fe7c6c 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -807,11 +807,11 @@ static int cortex_a_internal_restore(struct target *target, int current,
                armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true;
 
                /* Make sure we are in Thumb mode */
-               buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
-                       buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
+               buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0, 32,
+                       buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_XPSR].value, 0,
                        32) | (1 << 24));
-               armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = true;
-               armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = true;
+               armv7m->core_cache->reg_list[ARMV7M_XPSR].dirty = true;
+               armv7m->core_cache->reg_list[ARMV7M_XPSR].valid = true;
        }
 #endif
 

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 727d9ca07b2139728b263b1b5ee5a9e28369f7b8..8e9264b79ce5604eca3e71e2fd25a873eea9d115 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -775,7 +775,7 @@ static int cortex_m_examine_exception_reason(struct target *target)
 
 static int cortex_m_debug_entry(struct target *target)
 {
-       uint32_t xPSR;
+       uint32_t xpsr;
        int retval;
        struct cortex_m_common *cortex_m = target_to_cm(target);
        struct armv7m_common *armv7m = &cortex_m->armv7m;
@@ -826,11 +826,11 @@ static int cortex_m_debug_entry(struct target *target)
                return retval;
 
        r = arm->cpsr;
-       xPSR = buf_get_u32(r->value, 0, 32);
+       xpsr = buf_get_u32(r->value, 0, 32);
 
        /* Are we in an exception handler */
-       if (xPSR & 0x1FF) {
-               armv7m->exception_number = (xPSR & 0x1FF);
+       if (xpsr & 0x1FF) {
+               armv7m->exception_number = (xpsr & 0x1FF);
 
                arm->core_mode = ARM_MODE_HANDLER;
                arm->map = armv7m_msp_reg_map;

diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 748905691d065e66114e9658066ca2f53ac69b3e..d3a16cd9b8194d902ce0147e2854d3f11314a023 100644 (file)
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -231,7 +231,7 @@ static int adapter_debug_entry(struct target *target)
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct arm *arm = &armv7m->arm;
        struct reg *r;
-       uint32_t xPSR;
+       uint32_t xpsr;
        int retval;
 
        /* preserve the DCRDR across halts */
@@ -249,11 +249,11 @@ static int adapter_debug_entry(struct target *target)
        adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
 
        r = arm->cpsr;
-       xPSR = buf_get_u32(r->value, 0, 32);
+       xpsr = buf_get_u32(r->value, 0, 32);
 
        /* Are we in an exception handler */
-       if (xPSR & 0x1FF) {
-               armv7m->exception_number = (xPSR & 0x1FF);
+       if (xpsr & 0x1FF) {
+               armv7m->exception_number = (xpsr & 0x1FF);
 
                arm->core_mode = ARM_MODE_HANDLER;
                arm->map = armv7m_msp_reg_map;