And update doc accordingly. That EmbeddedICE register was
introduced for ARM9TDMI and then carried forward into most
new chips that use EmbeddedICE.
VERY EARLY Cortex-A8 and ARMv7A support
Updated BeagleBoard.org hardware support
New commands for use with XScale processors: "xscale vector_table"
VERY EARLY Cortex-A8 and ARMv7A support
Updated BeagleBoard.org hardware support
New commands for use with XScale processors: "xscale vector_table"
+ ARM9
+ name change: "arm9 vector_catch" not "arm9tdmi vector_catch"
ARM11
single stepping support for i.MX31
bugfix for missing "arm11" prefix on "arm11 memwrite ..."
ARM11
single stepping support for i.MX31
bugfix for missing "arm11" prefix on "arm11 memwrite ..."
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM7/9:
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM7/9:
- - clean up "arm9tdmi vector_catch". Should be available for other arm9
- (e.g. arm926ejs) and some(???) arm7 cores. @par
-https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
+ - clean up "arm9tdmi vector_catch". Available for some arm7 cores? @par
+https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
that the @code{reset-init} event handler does.
@item
that the @code{reset-init} event handler does.
@item
-Likewise, the @command{arm9tdmi vector_catch} command (or
+Likewise, the @command{arm9 vector_catch} command (or
@cindex vector_catch
its siblings @command{xscale vector_catch}
and @command{cortex_m3 vector_catch}) can be a timesaver
@cindex vector_catch
its siblings @command{xscale vector_catch}
and @command{cortex_m3 vector_catch}) can be a timesaver
This is a software breakpoint, unless @option{hw} is specified
in which case it will be a hardware breakpoint.
This is a software breakpoint, unless @option{hw} is specified
in which case it will be a hardware breakpoint.
-(@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
+(@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
for similar mechanisms that do not consume hardware breakpoints.)
@end deffn
for similar mechanisms that do not consume hardware breakpoints.)
@end deffn
integer processors.
Such cores include the ARM920T, ARM926EJ-S, and ARM966.
integer processors.
Such cores include the ARM920T, ARM926EJ-S, and ARM966.
-For historical reasons, one command shared by these cores starts
-with the @command{arm9tdmi} prefix.
-This is true even for ARM9E based processors, which implement the
-ARMv5TE architecture instead of ARMv4T.
-
@c 9-june-2009: tried this on arm920t, it didn't work.
@c no-params always lists nothing caught, and that's how it acts.
@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
@c versions have different rules about when they commit writes.
@c 9-june-2009: tried this on arm920t, it didn't work.
@c no-params always lists nothing caught, and that's how it acts.
@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
@c versions have different rules about when they commit writes.
-@anchor{arm9tdmi vector_catch}
-@deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
+@anchor{arm9 vector_catch}
+@deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
@cindex vector_catch
Vector Catch hardware provides a sort of dedicated breakpoint
for hardware events such as reset, interrupt, and abort.
@cindex vector_catch
Vector Catch hardware provides a sort of dedicated breakpoint
for hardware events such as reset, interrupt, and abort.
command_t *arm9tdmi_cmd;
retval = arm7_9_register_commands(cmd_ctx);
command_t *arm9tdmi_cmd;
retval = arm7_9_register_commands(cmd_ctx);
- arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi",
+ arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9",
- "arm9tdmi specific commands");
+ "arm9 specific commands");
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
- "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] - separate vectors to catch by space");
-
-
+ "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ...");
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