Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
# General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGU signal for OMAP353x
# General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGU signal for OMAP353x
- $target mww 0x5401d030 0x00002000
+ $target mww phys 0x5401d030 0x00002000
}
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
}
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10; halt; halt }
+$_TARGETNAME configure -event "reset-start" { adapter_khz 10}
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# would issue. RST_DPLL3 (4) is a cold reset.
set PRM_RSTCTRL 0x48307250
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# would issue. RST_DPLL3 (4) is a cold reset.
set PRM_RSTCTRL 0x48307250
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME; adapter_khz 1000"
$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME; adapter_khz 1000"
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