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John McCarthy <jgmcc@magma.ca> cleans up the usage of the
authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Tue, 14 Oct 2008 06:21:17 +0000 (06:21 +0000)
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Tue, 14 Oct 2008 06:21:17 +0000 (06:21 +0000)
ejtag_info->ejtag_ctrl variable.  It was being overwritten by the value read back from the EJTAG CONTROL register.  Because of the way this register works you do not want to use the value returned to write the register, you always want to write the bits explicitly.

The second patch just reduces the DMA retries to 0 in anticipation of removing the retry code altogether.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1049 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/mips32_dmaacc.c patch | blob | history
src/target/mips32_dmaacc.h patch | blob | history
src/target/mips32_pracc.c patch | blob | history
src/target/mips_ejtag.c patch | blob | history
src/target/mips_m4k.c patch | blob | history

diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index 7ca6c29add48d2f845d23a4f98b05c76b1414878..ddcfb97d781c3cf9f73f7d1c0bac6f3b256ce404 100644 (file)
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -44,7 +44,7 @@
 static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
 {
        u32 v;
-       u32 ctrl_reg;
+       u32 ejtag_ctrl;
        int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read:
@@ -56,14 +56,14 @@ begin_ejtag_dma_read:
 
        // Initiate DMA Read & set DSTRT
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        // Wait for DSTRT to Clear
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
        // Read Data
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -71,9 +71,9 @@ begin_ejtag_dma_read:
 
        // Clear DMA & Check DERR
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
                        printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
@@ -88,7 +88,7 @@ begin_ejtag_dma_read:
 static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
 {
        u32 v;
-       u32 ctrl_reg;
+       u32 ejtag_ctrl;
        int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_h:
@@ -100,14 +100,14 @@ begin_ejtag_dma_read_h:
 
        // Initiate DMA Read & set DSTRT
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        // Wait for DSTRT to Clear
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
        // Read Data
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -115,9 +115,9 @@ begin_ejtag_dma_read_h:
 
        // Clear DMA & Check DERR
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
                        printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
@@ -136,7 +136,7 @@ begin_ejtag_dma_read_h:
 static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
 {
        u32 v;
-       u32 ctrl_reg;
+       u32 ejtag_ctrl;
        int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_b:
@@ -148,14 +148,14 @@ begin_ejtag_dma_read_b:
 
        // Initiate DMA Read & set DSTRT
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        // Wait for DSTRT to Clear
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
        // Read Data
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
@@ -163,9 +163,9 @@ begin_ejtag_dma_read_b:
 
        // Clear DMA & Check DERR
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
                        printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
@@ -188,7 +188,7 @@ begin_ejtag_dma_read_b:
 static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
        u32 v;
-       u32 ctrl_reg;
+       u32 ejtag_ctrl;
        int   retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_write:
@@ -205,20 +205,20 @@ begin_ejtag_dma_write:
 
        // Initiate DMA Write & set DSTRT
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        // Wait for DSTRT to Clear
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
        // Clear DMA & Check DERR
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
                        printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
@@ -233,7 +233,7 @@ begin_ejtag_dma_write:
 static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
        u32 v;
-       u32 ctrl_reg;
+       u32 ejtag_ctrl;
        int   retries = RETRY_ATTEMPTS;
 
 
@@ -255,20 +255,20 @@ begin_ejtag_dma_write_h:
 
        // Initiate DMA Write & set DSTRT
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        // Wait for DSTRT to Clear
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
        // Clear DMA & Check DERR
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
                        printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
@@ -283,7 +283,7 @@ begin_ejtag_dma_write_h:
 static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
 {
        u32 v;
-       u32 ctrl_reg;
+       u32 ejtag_ctrl;
        int   retries = RETRY_ATTEMPTS;
 
 
@@ -306,20 +306,20 @@ begin_ejtag_dma_write_b:
 
        // Initiate DMA Write & set DSTRT
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
        // Wait for DSTRT to Clear
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
        // Clear DMA & Check DERR
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
                        printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
diff --git a/src/target/mips32_dmaacc.h b/src/target/mips32_dmaacc.h
index 2383ee9f99cb4ae55248e86aa6c9087ce0890fa6..443fef805f962c75a3eca4fe334d4fbb8912a22e 100644 (file)
--- a/src/target/mips32_dmaacc.h
+++ b/src/target/mips32_dmaacc.h
@@ -32,7 +32,7 @@
 #define EJTAG_CTRL_DMA_WORD        0x00000100
 #define EJTAG_CTRL_DMA_TRIPLEBYTE  0x00000180
 
-#define RETRY_ATTEMPTS 4
+#define RETRY_ATTEMPTS 0
 
 extern int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
 extern int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf);
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 5f8b0cee5bcc6c1708a30d6a26b96bdf9f9b0183..8e17e05c71c71e157b2f9dc9e23b9cc9c348c90d 100644 (file)
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -47,7 +47,7 @@ static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl)
        while (1) 
        {
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-               ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+               ejtag_ctrl = ejtag_info->ejtag_ctrl;
                mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
                if (ejtag_ctrl & EJTAG_CTRL_PRACC)
                        break;
@@ -61,8 +61,9 @@ static int wait_for_pracc_rw(mips_ejtag_t *ejtag_info, u32 *ctrl)
 
 static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address)
 {
+       mips_ejtag_t *ejtag_info = ctx->ejtag_info;
        int offset;
-       u32 ctrl, data;
+       u32 ejtag_ctrl, data;
 
        if ((address >= MIPS32_PRACC_PARAM_IN)
                && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
@@ -102,25 +103,26 @@ static int mips32_pracc_exec_read(mips32_pracc_context *ctx, u32 address)
        mips_ejtag_drscan_32(ctx->ejtag_info, &data);
 
        /* Clear the access pending bit (let the processor eat!) */
-       ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+       ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
        mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
-       mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl);
+       mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
        
        return ERROR_OK;
 }
 
 static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address)
 {
-       u32 ctrl,data;
+       u32 ejtag_ctrl,data;
        int offset;
+       mips_ejtag_t *ejtag_info = ctx->ejtag_info;
        
        mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ctx->ejtag_info, &data);
        
        /* Clear access pending bit */
-       ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
+       ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
        mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
-       mips_ejtag_drscan_32(ctx->ejtag_info, &ctrl);
+       mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
        
        if ((address >= MIPS32_PRACC_PARAM_IN)
                && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4))
@@ -150,7 +152,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, u32 address)
 
 int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int num_param_in, u32 *param_in, int num_param_out, u32 *param_out, int cycle)
 {
-       u32 ctrl;
+       u32 ejtag_ctrl;
        u32 address, data;
        mips32_pracc_context ctx;
        int retval;
@@ -167,7 +169,7 @@ int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int nu
        
        while (1)
        {
-               if ((retval = wait_for_pracc_rw(ejtag_info, &ctrl)) != ERROR_OK)
+               if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
                        return retval;
                
                address = data = 0;
@@ -175,7 +177,7 @@ int mips32_pracc_exec( mips_ejtag_t *ejtag_info, int code_len, u32 *code, int nu
                mips_ejtag_drscan_32(ejtag_info, &address);
                
                /* Check for read or write */
-               if (ctrl & EJTAG_CTRL_PRNW)
+               if (ejtag_ctrl & EJTAG_CTRL_PRNW)
                {
                        if ((retval = mips32_pracc_exec_write(&ctx, address)) != ERROR_OK)
                                return retval;
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 6e6bd934931387fff2bd6f9207c3d2a110e2c55e..09470b0804a66c0d5aae776e12f9301bed56b6eb 100644 (file)
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -194,18 +194,19 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step)
 
 int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info)
 {
+       u32 ejtag_ctrl;
        jtag_add_end_state(TAP_RTI);
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
        
        /* set debug break bit */
-       ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV | EJTAG_CTRL_JTAGBRK;
-       mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+       ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
        
        /* break bit will be cleared by hardware */
-       ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
-       mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
-       LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_info->ejtag_ctrl);
-       if((ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       LOG_DEBUG("ejtag_ctrl: 0x%8.8x", ejtag_ctrl);
+       if((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
                LOG_DEBUG("Failed to enter Debug Mode!");
        
        return ERROR_OK;
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 3508ebd16f058ea97dbcaef4a6a376b65865f263..be7f59ec8c38ab7e2bd334605985f110b59c14a9 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -132,13 +132,14 @@ int mips_m4k_poll(target_t *target)
        int retval;
        mips32_common_t *mips32 = target->arch_info;
        mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+       u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
        
        /* read ejtag control reg */
        jtag_add_end_state(TAP_RTI);
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
        
-       if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
+       if (ejtag_ctrl & EJTAG_CTRL_BRKST)
        {
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
@@ -167,19 +168,19 @@ int mips_m4k_poll(target_t *target)
                target->state = TARGET_RUNNING;
        }
        
-       if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
+       if (ejtag_ctrl & EJTAG_CTRL_ROCC)
        {
                /* we have detected a reset, clear flag
                 * otherwise ejtag will not work */
                jtag_add_end_state(TAP_RTI);
-               ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
+               ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
                
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
                LOG_DEBUG("Reset Detected");
        }
        
-//     LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
+//     LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
        
        return ERROR_OK;
 }
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