Don't expose the RDTR register through the register cache any
more. If anyone wants Tcl scripts to be able to use DCC based
communication with app code in the target, this wouldn't do it.
Bugfix: don't trust the Tcl-accessible version of DSCR to
flag whether RDTR needs to be restored when resuming.
/* debug regs */
ARM11_REGISTER_DSCR,
ARM11_REGISTER_WDTR,
/* debug regs */
ARM11_REGISTER_DSCR,
ARM11_REGISTER_WDTR,
/* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
/* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
- {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
};
enum arm11_regcache_ids
{
ARM11_RC_DSCR,
ARM11_RC_WDTR,
};
enum arm11_regcache_ids
{
ARM11_RC_DSCR,
ARM11_RC_WDTR,
return retval;
/* maybe save rDTR */
return retval;
/* maybe save rDTR */
-
- /* check rDTRfull in DSCR */
-
- if (dscr & ARM11_DSCR_RDTR_FULL)
+ arm11->is_rdtr_saved = !!(dscr & ARM11_DSCR_RDTR_FULL);
+ if (arm11->is_rdtr_saved)
{
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
{
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
- retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
+ retval = arm11_run_instr_data_from_core_via_r0(arm11,
+ 0xEE100E15, &arm11->saved_rdtr);
if (retval != ERROR_OK)
return retval;
}
if (retval != ERROR_OK)
return retval;
}
- else
- {
- arm11->reg_list[ARM11_RC_RDTR].valid = 0;
- }
/* REVISIT Now that we've saved core state, there's may also
* be MMU and cache state to care about ...
/* REVISIT Now that we've saved core state, there's may also
* be MMU and cache state to care about ...
- if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
+ if (arm11->is_rdtr_saved)
{
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
{
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
uint8_t Ready = 0; /* ignored */
uint8_t Valid = 0; /* ignored */
uint8_t Ready = 0; /* ignored */
uint8_t Valid = 0; /* ignored */
- arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
+ arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
+ NULL, chain5_fields + 0);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
#include "armv4_5.h"
#include "arm_dpm.h"
#include "armv4_5.h"
#include "arm_dpm.h"
-#define ARM11_REGCACHE_COUNT 3
+#define ARM11_REGCACHE_COUNT 2
#define ARM11_TAP_DEFAULT TAP_INVALID
#define ARM11_TAP_DEFAULT TAP_INVALID
uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */
uint32_t last_dscr; /**< Last retrieved DSCR value;
Use only for debug message generation */
+ uint32_t saved_rdtr;
+
+ bool is_rdtr_saved;
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save debug state */
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save debug state */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)