Remove misleading typedef and redundant suffix from struct arm7_9_common.
16 files changed:
{
int retval;
armv4_5_common_t *armv4_5;
{
int retval;
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
struct ocl_priv *ocl;
if (argc < 6)
struct ocl_priv *ocl;
if (argc < 6)
{
struct str9xpec_flash_controller *str9xpec_info;
armv4_5_common_t *armv4_5 = NULL;
{
struct str9xpec_flash_controller *str9xpec_info;
armv4_5_common_t *armv4_5 = NULL;
- arm7_9_common_t *arm7_9 = NULL;
+ struct arm7_9_common *arm7_9 = NULL;
arm_jtag_t *jtag_info = NULL;
if (argc < 6)
arm_jtag_t *jtag_info = NULL;
if (argc < 6)
struct arm720t_common *arm720t, struct jtag_tap *tap)
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
struct arm720t_common *arm720t, struct jtag_tap *tap)
{
arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
- arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common;
arm7tdmi_init_arch_info(target, arm7tdmi, tap);
arm7tdmi_init_arch_info(target, arm7tdmi, tap);
* @param arm7_9 Pointer to the common struct for an ARM7/9 target
* @return JTAG error status after executing queue
*/
* @param arm7_9 Pointer to the common struct for an ARM7/9 target
* @return JTAG error status after executing queue
*/
-static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
+static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
{
LOG_DEBUG("-");
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
{
LOG_DEBUG("-");
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
* @param arm7_9 Pointer to the common struct for an ARM7/9 target
* @param breakpoint Pointer to the breakpoint to be used as a watchpoint
*/
* @param arm7_9 Pointer to the common struct for an ARM7/9 target
* @param breakpoint Pointer to the breakpoint to be used as a watchpoint
*/
-static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
+static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, breakpoint_t *breakpoint)
{
if (!arm7_9->wp0_used)
{
{
if (!arm7_9->wp0_used)
{
* @return Error codes if there is a problem finding a watchpoint or the result
* of executing the JTAG queue
*/
* @return Error codes if there is a problem finding a watchpoint or the result
* of executing the JTAG queue
*/
-static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
+static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
{
if (arm7_9->sw_breakpoints_added)
{
{
if (arm7_9->sw_breakpoints_added)
{
*/
int arm7_9_setup(target_t *target)
{
*/
int arm7_9_setup(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return arm7_9_clear_watchpoints(arm7_9);
}
return arm7_9_clear_watchpoints(arm7_9);
}
* targets
* @return ERROR_OK if successful
*/
* targets
* @return ERROR_OK if successful
*/
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
+int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p)
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
/* FIXME stop using this routine; just target_to_arm7_9() and
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
/* FIXME stop using this routine; just target_to_arm7_9() and
*/
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
*/
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
int retval = ERROR_OK;
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
breakpoint->unique_id,
LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
breakpoint->unique_id,
*/
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
*/
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
{
if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
{
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int rw_mask = 1;
uint32_t mask;
int rw_mask = 1;
uint32_t mask;
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
*/
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
*/
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_execute_sys_speed(struct target_s *target)
{
int retval;
int arm7_9_execute_sys_speed(struct target_s *target)
{
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
static int set = 0;
static uint8_t check_value[4], check_mask[4];
static int set = 0;
static uint8_t check_value[4], check_mask[4];
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
*/
int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
*/
int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t *data;
int retval = ERROR_OK;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t *data;
int retval = ERROR_OK;
target_t *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
target_t *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
int arm7_9_poll(target_t *target)
{
int retval;
int arm7_9_poll(target_t *target)
{
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* read debug status register */
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* read debug status register */
*/
int arm7_9_assert_reset(target_t *target)
{
*/
int arm7_9_assert_reset(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
LOG_DEBUG("target->state: %s",
target_state_name(target));
*/
int arm7_9_clear_halt(target_t *target)
{
*/
int arm7_9_clear_halt(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
*/
int arm7_9_soft_reset_halt(struct target_s *target)
{
*/
int arm7_9_soft_reset_halt(struct target_s *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
uint32_t r0_thumb, pc_thumb;
uint32_t cpsr;
int retval;
uint32_t r0_thumb, pc_thumb;
uint32_t cpsr;
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
LOG_DEBUG("-");
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
LOG_DEBUG("-");
*/
int arm7_9_restore_context(target_t *target)
{
*/
int arm7_9_restore_context(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *reg;
armv4_5_core_reg_t *reg_arch_info;
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *reg;
armv4_5_core_reg_t *reg_arch_info;
*/
int arm7_9_restart_core(struct target_s *target)
{
*/
int arm7_9_restart_core(struct target_s *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* set RESTART instruction */
int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = target->breakpoints;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
{
void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t current_pc;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
void arm7_9_disable_eice_step(target_t *target)
{
void arm7_9_disable_eice_step(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = NULL;
int err, retval;
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
breakpoint_t *breakpoint = NULL;
int err, retval;
uint32_t* reg_p[16];
uint32_t value;
int retval;
uint32_t* reg_p[16];
uint32_t value;
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
{
uint32_t reg[16];
int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
{
uint32_t reg[16];
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16];
uint32_t num_accesses = 0;
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t reg[16];
uint32_t num_accesses = 0;
int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int i;
if (!arm7_9->dcc_downloads)
int i;
if (!arm7_9->dcc_downloads)
int retval;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
int retval;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
int retval;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
int retval;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
int num;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
int num;
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
-int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
+int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
/**
* Structure for items that are common between both ARM7 and ARM9 targets.
*/
/**
* Structure for items that are common between both ARM7 and ARM9 targets.
*/
-typedef struct arm7_9_common_s
{
struct arm armv4_5_common;
uint32_t common_magic;
{
struct arm armv4_5_common;
uint32_t common_magic;
void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
-static inline struct arm7_9_common_s *
+static inline struct arm7_9_common *
target_to_arm7_9(struct target_s *target)
{
target_to_arm7_9(struct target_s *target)
{
- return container_of(target->arch_info, struct arm7_9_common_s,
+ return container_of(target->arch_info, struct arm7_9_common,
int arm7_9_execute_sys_speed(struct target_s *target);
int arm7_9_execute_sys_speed(struct target_s *target);
-int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
+int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9);
+int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p);
#endif /* ARM7_9_COMMON_H */
#endif /* ARM7_9_COMMON_H */
static int arm7tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
static int arm7tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
static void arm7tdmi_change_to_arm(target_t *target,
uint32_t *r0, uint32_t *pc)
{
static void arm7tdmi_change_to_arm(target_t *target,
uint32_t *r0, uint32_t *pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
uint32_t mask, uint32_t* core_regs[16])
{
int i;
uint32_t mask, uint32_t* core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
uint32_t mask, void* buffer, int size)
{
int i;
uint32_t mask, void* buffer, int size)
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
static void arm7tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
static void arm7tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
uint32_t mask, uint32_t core_regs[16])
{
int i;
uint32_t mask, uint32_t core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
static void arm7tdmi_load_hword_reg(target_t *target, int num)
{
static void arm7tdmi_load_hword_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
static void arm7tdmi_load_byte_reg(target_t *target, int num)
{
static void arm7tdmi_load_byte_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
static void arm7tdmi_store_hword_reg(target_t *target, int num)
{
static void arm7tdmi_store_hword_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
static void arm7tdmi_store_byte_reg(target_t *target, int num)
{
static void arm7tdmi_store_byte_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
static void arm7tdmi_write_pc(target_t *target, uint32_t pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
static void arm7tdmi_branch_resume(target_t *target)
{
static void arm7tdmi_branch_resume(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
static void arm7tdmi_branch_resume_thumb(target_t *target)
{
static void arm7tdmi_branch_resume_thumb(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int arm7tdmi_examine(struct target_s *target)
{
int arm7tdmi_examine(struct target_s *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, struct jtag_tap *tap)
{
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, struct jtag_tap *tap)
{
- struct arm7_9_common_s *arm7_9 = &arm7tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common;
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
*/
typedef struct arm7tdmi_common_s
{
*/
typedef struct arm7tdmi_common_s
{
- arm7_9_common_t arm7_9_common;
+ struct arm7_9_common arm7_9_common;
} arm7tdmi_common_t;
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, struct jtag_tap *tap);
} arm7tdmi_common_t;
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, struct jtag_tap *tap);
{
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
{
int retval = ERROR_OK;
struct arm920t_common *arm920t = target_to_arm920(target);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
- arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
struct arm920t_common *arm920t = target_to_arm920(target);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
uint32_t cp15c15;
uint32_t cp15_ctrl, cp15_ctrl_saved;
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
int retval = ERROR_OK;
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
uint32_t CRn, uint32_t CRm, uint32_t value)
{
int retval = ERROR_OK;
uint32_t CRn, uint32_t CRm, uint32_t value)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
struct scan_field fields[4];
static int arm926ejs_examine_debug_reason(target_t *target)
{
static int arm926ejs_examine_debug_reason(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int debug_reason;
int retval;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int debug_reason;
int retval;
{
int retval = ERROR_OK;
struct arm926ejs_common_s *arm926ejs = target_to_arm926(target);
{
int retval = ERROR_OK;
struct arm926ejs_common_s *arm926ejs = target_to_arm926(target);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
- arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
- arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
arm9tdmi_init_arch_info(target, arm9tdmi, tap);
arm9tdmi_init_arch_info(target, arm9tdmi, tap);
static int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
static int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value)
{
int retval = ERROR_OK;
int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
struct scan_field fields[3];
uint8_t reg_addr_buf = reg_addr & 0x3f;
int arm9tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
int arm9tdmi_examine_debug_reason(target_t *target)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
uint32_t *r0, uint32_t *pc)
{
int retval = ERROR_OK;
uint32_t *r0, uint32_t *pc)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
uint32_t mask, uint32_t* core_regs[16])
{
int i;
uint32_t mask, uint32_t* core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
uint32_t mask, void* buffer, int size)
{
int i;
uint32_t mask, void* buffer, int size)
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
static void arm9tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
static void arm9tdmi_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
uint32_t mask, uint32_t core_regs[16])
{
int i;
uint32_t mask, uint32_t core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
{
void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
void arm9tdmi_load_hword_reg(target_t *target, int num)
{
void arm9tdmi_load_hword_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
void arm9tdmi_load_byte_reg(target_t *target, int num)
{
void arm9tdmi_load_byte_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
{
void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
void arm9tdmi_store_hword_reg(target_t *target, int num)
{
void arm9tdmi_store_hword_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
void arm9tdmi_store_byte_reg(target_t *target, int num)
{
void arm9tdmi_store_byte_reg(target_t *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
{
static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
void arm9tdmi_branch_resume(target_t *target)
{
void arm9tdmi_branch_resume(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
{
void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (arm7_9->has_single_step)
{
if (arm7_9->has_single_step)
{
void arm9tdmi_disable_single_step(target_t *target)
{
void arm9tdmi_disable_single_step(target_t *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (arm7_9->has_single_step)
{
if (arm7_9->has_single_step)
{
int arm9tdmi_examine(struct target_s *target)
{
int retval;
int arm9tdmi_examine(struct target_s *target)
{
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (!target_was_examined(target))
{
if (!target_was_examined(target))
{
int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
{
armv4_5_common_t *armv4_5;
int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
{
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common;
arm7_9 = &arm9tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common;
COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
{
target_t *target = get_current_target(cmd_ctx);
COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
{
target_t *target = get_current_target(cmd_ctx);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
reg_t *vector_catch;
uint32_t vector_catch_value;
reg_t *vector_catch;
uint32_t vector_catch_value;
*/
typedef struct arm9tdmi_common_s
{
*/
typedef struct arm9tdmi_common_s
{
- arm7_9_common_t arm7_9_common;
+ struct arm7_9_common arm7_9_common;
} arm9tdmi_common_t;
typedef struct arm9tdmi_vector_s
} arm9tdmi_common_t;
typedef struct arm9tdmi_vector_s
* hardware support for vector_catch, single stepping, and monitor mode.
*/
reg_cache_t *
* hardware support for vector_catch, single stepping, and monitor mode.
*/
reg_cache_t *
-embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
+embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9)
{
int retval;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
{
int retval;
reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
int embeddedice_setup(target_t *target)
{
int retval;
int embeddedice_setup(target_t *target)
{
int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* Explicitly disable monitor mode. For now we only support halting
* debug ... we don't know how to talk with a resident debug monitor
/* Explicitly disable monitor mode. For now we only support halting
* debug ... we don't know how to talk with a resident debug monitor
} embeddedice_reg_t;
reg_cache_t* embeddedice_build_reg_cache(target_t *target,
} embeddedice_reg_t;
reg_cache_t* embeddedice_build_reg_cache(target_t *target,
- arm7_9_common_t *arm7_9);
+ struct arm7_9_common *arm7_9);
int embeddedice_setup(target_t *target);
int embeddedice_setup(target_t *target);
uint32_t mask, uint32_t* core_regs[16])
{
int i;
uint32_t mask, uint32_t* core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
uint32_t mask, void* buffer, int size)
{
int i;
uint32_t mask, void* buffer, int size)
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
static void fa526_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
static void fa526_write_xpsr_im8(target_t *target,
uint8_t xpsr_im, int rot, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
uint32_t mask, uint32_t core_regs[16])
{
int i;
uint32_t mask, uint32_t core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
static void fa526_write_pc(target_t *target, uint32_t pc)
{
static void fa526_write_pc(target_t *target, uint32_t pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
static int fa526_init_arch_info_2(target_t *target,
arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
{
static int fa526_init_arch_info_2(target_t *target,
arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
{
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common;
arm7_9 = &arm9tdmi->arm7_9_common;
struct arm920t_common *arm920t, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
struct arm920t_common *arm920t, struct jtag_tap *tap)
{
arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
- arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
+ struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common;
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
*/
int feroceon_assert_reset(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
int feroceon_assert_reset(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int ud = arm7_9->use_dbgrq;
arm7_9->use_dbgrq = 0;
int ud = arm7_9->use_dbgrq;
arm7_9->use_dbgrq = 0;
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/*
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
/*
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
{
int i;
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
void feroceon_branch_resume(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_branch_resume(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
LOG_DEBUG("-");
armv4_5_common_t *armv4_5 = target->arch_info;
LOG_DEBUG("-");
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int err;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
int err;
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
void feroceon_set_dbgrq(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_set_dbgrq(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* set a breakpoint there */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
/* set a breakpoint there */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
void feroceon_disable_single_step(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_disable_single_step(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
uint32_t i;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
uint32_t i;
void feroceon_common_setup(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
void feroceon_common_setup(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* override some insn sequence functions */
arm7_9->change_to_arm = feroceon_change_to_arm;
/* override some insn sequence functions */
arm7_9->change_to_arm = feroceon_change_to_arm;
int feroceon_examine(struct target_s *target)
{
armv4_5_common_t *armv4_5;
int feroceon_examine(struct target_s *target)
{
armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
+ struct arm7_9_common *arm7_9;
int retval;
retval = arm9tdmi_examine(target);
int retval;
retval = arm9tdmi_examine(target);
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