int pic32mx_erase(struct flash_bank_s *bank, int first, int last);
int pic32mx_protect(struct flash_bank_s *bank, int set, int first, int last);
int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr);
+int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word);
int pic32mx_probe(struct flash_bank_s *bank);
int pic32mx_auto_probe(struct flash_bank_s *bank);
int pic32mx_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int pic32mx_protect_check(struct flash_bank_s *bank)
{
target_t *target = bank->target;
- pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
u32 devcfg0;
int s;
return ERROR_TARGET_NOT_HALTED;
}
-#if 0
if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))
{
+ LOG_DEBUG("Erasing entire program flash");
status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
if( status & NVMCON_NVMERR )
return ERROR_FLASH_OPERATION_FAILED;
return ERROR_FLASH_OPERATION_FAILED;
return ERROR_OK;
}
-#endif
for (i = first; i <= last; i++)
{
- target_write_u32(target, PIC32MX_NVMADDR, bank->base + bank->sectors[i].offset);
+ if(bank->base >= PIC32MX_KSEG1_PGM_FLASH)
+ target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(bank->base + bank->sectors[i].offset));
+ else
+ target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(bank->base + bank->sectors[i].offset));
status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
int pic32mx_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
- pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
target_t *target = bank->target;
- u32 buffer_size = 8192;
+ u32 buffer_size = 512;
working_area_t *source;
u32 address = bank->base + offset;
- reg_param_t reg_params[4];
+ int retval = ERROR_OK;
#if 0
+ pic32mx_flash_bank_t *pic32mx_info = bank->driver_priv;
armv7m_algorithm_t armv7m_info;
- int retval = ERROR_OK;
u8 pic32mx_flash_write_code[] = {
/* write: */
if ((retval=target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code))!=ERROR_OK)
return retval;
+#endif
/* memory buffer */
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
+ if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
{
- buffer_size /= 2;
- if (buffer_size <= 256)
- {
- /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
- if (pic32mx_info->write_algorithm)
- target_free_working_area(target, pic32mx_info->write_algorithm);
-
- LOG_WARNING("no large enough working area available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
- };
-
- armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
- armv7m_info.core_mode = ARMV7M_MODE_ANY;
+#if 0
+ /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
+ if (pic32mx_info->write_algorithm)
+ target_free_working_area(target, pic32mx_info->write_algorithm);
+#endif
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
- init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
- init_reg_param(®_params[3], "r3", 32, PARAM_IN);
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- while (count > 0)
+ while (count >= buffer_size/4)
{
- u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
+ u32 status;
- if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
+ if ((retval = target_write_buffer(target, source->address, buffer_size, buffer))!=ERROR_OK) {
+ LOG_ERROR("Failed to write row buffer (%d words) to RAM", buffer_size/4);
break;
+ }
+#if 0
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
- buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+ buf_set_u32(reg_params[2].value, 0, 32, buffer_size/4);
if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \
pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
+#endif
+ status = pic32mx_write_row(bank, address, source->address);
+ if( status & NVMCON_NVMERR ) {
+ LOG_ERROR("Flash write error NVMERR (status=0x%08x)", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+ if( status & NVMCON_LVDERR ) {
+ LOG_ERROR("Flash write error LVDERR (status=0x%08x)", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
- buffer += thisrun_count * 2;
- address += thisrun_count * 2;
- count -= thisrun_count;
+ buffer += buffer_size;
+ address += buffer_size;
+ count -= buffer_size/4;
}
target_free_working_area(target, source);
- target_free_working_area(target, pic32mx_info->write_algorithm);
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- destroy_reg_param(®_params[3]);
+ while(count > 0)
+ {
+ u32 status;
+
+ status = pic32mx_write_word(bank, address, *(u32*)buffer);
+ if( status & NVMCON_NVMERR ) {
+ LOG_ERROR("Flash write error NVMERR (status=0x%08x)", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+ if( status & NVMCON_LVDERR ) {
+ LOG_ERROR("Flash write error LVDERR (status=0x%08x)", status);
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ break;
+ }
+
+ buffer += 4;
+ address += 4;
+ count--;
+ }
return retval;
-#else
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-#endif
}
int pic32mx_write_word(struct flash_bank_s *bank, u32 address, u32 word)
{
target_t *target = bank->target;
- target_write_u32(target, PIC32MX_NVMADDR, address);
+ if(bank->base >= PIC32MX_KSEG1_PGM_FLASH)
+ target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
+ else
+ target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
target_write_u32(target, PIC32MX_NVMDATA, word);
return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
}
-int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+/*
+ * Write a 128 word (512 byte) row to flash address from RAM srcaddr.
+ */
+int pic32mx_write_row(struct flash_bank_s *bank, u32 address, u32 srcaddr)
{
target_t *target = bank->target;
+
+ LOG_DEBUG("addr: 0x%08x srcaddr: 0x%08x", address, srcaddr);
+
+ if(address >= PIC32MX_KSEG1_PGM_FLASH)
+ target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
+ else
+ target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
+ if(srcaddr >= PIC32MX_KSEG1_RAM)
+ target_write_u32(target, PIC32MX_NVMSRCADDR, KS1Virt2Phys(srcaddr));
+ else
+ target_write_u32(target, PIC32MX_NVMSRCADDR, KS0Virt2Phys(srcaddr));
+
+ return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
+}
+
+int pic32mx_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
u32 words_remaining = (count / 4);
u32 bytes_remaining = (count & 0x00000003);
u32 address = bank->base + offset;
{
flash_bank_t *bank;
u32 address, value;
- int i;
int status, res;
if (argc != 3)
/* pic32mx memory locations */
#define PIC32MX_KUSEG_PGM_FLASH 0x7D000000
-#define PIC32MX_KUSEG_RAM 0x7F000000
+#define PIC32MX_KUSEG_RAM 0x7F000000
-#define PIC32MX_KSEG0_RAM 0x80000000
+#define PIC32MX_KSEG0_RAM 0x80000000
#define PIC32MX_KSEG0_PGM_FLASH 0x9D000000
#define PIC32MX_KSEG0_BOOT_FLASH 0x9FC00000
-#define PIC32MX_KSEG1_RAM 0xA0000000
+#define PIC32MX_KSEG1_RAM 0xA0000000
#define PIC32MX_KSEG1_PGM_FLASH 0xBD000000
#define PIC32MX_KSEG1_PERIPHERAL 0xBF800000
#define PIC32MX_KSEG1_BOOT_FLASH 0xBFC00000
-#define PIC32MX_PHYS_RAM 0x00000000
+#define PIC32MX_PHYS_RAM 0x00000000
#define PIC32MX_PHYS_PGM_FLASH 0x1D000000
#define PIC32MX_PHYS_PERIPHERALS 0x1F800000
#define PIC32MX_PHYS_BOOT_FLASH 0x1FC00000
+/*
+ * Translate Virtual and Physical addresses.
+ * Note: These macros only work for KSEG0/KSEG1 addresses.
+ */
+#define KS1Virt2Phys(vaddr) ((vaddr)-0xA0000000)
+#define Phys2KS1Virt(paddr) ((paddr)+0xA0000000)
+#define KS0Virt2Phys(vaddr) ((vaddr)-0x80000000)
+#define Phys2KS0Virt(paddr) ((paddr)+0x80000000)
+
/* pic32mx configuration register locations */
#define PIC32MX_DEVCFG0 0xBFC02FFC
#define NVMCON_NVMERR (1<<13)
#define NVMCON_LVDERR (1<<12)
#define NVMCON_LVDSTAT (1<<11)
-#define NVMCON_OP_PFM_ERASE 0x5
+#define NVMCON_OP_PFM_ERASE 0x5
#define NVMCON_OP_PAGE_ERASE 0x4
-#define NVMCON_OP_ROW_PROG 0x3
-#define NVMCON_OP_WORD_PROG 0x1
-#define NVMCON_OP_NOP 0x0
+#define NVMCON_OP_ROW_PROG 0x3
+#define NVMCON_OP_WORD_PROG 0x1
+#define NVMCON_OP_NOP 0x0
#define PIC32MX_NVMKEY 0xBF80F410
#define PIC32MX_NVMADDR 0xBF80F420
case 2:
return mips32_pracc_read_mem16(ejtag_info, addr, count, (u16*)buf);
case 4:
- return mips32_pracc_read_mem32(ejtag_info, addr, count, (u32*)buf);
+ if(count==1)
+ return mips32_pracc_read_u32(ejtag_info, addr, (u32*)buf);
+ else
+ return mips32_pracc_read_mem32(ejtag_info, addr, count, (u32*)buf);
}
return ERROR_OK;
MIPS32_BEQ(0,10,9), /* beq 0, $10, end */
MIPS32_NOP,
- MIPS32_LW(12,0,9), /* lw $12,0($9), Load $12 with the word @mem[$9] */
- MIPS32_SW(12,0,11), /* sw $12,0($11) */
+ MIPS32_LW(8,0,9), /* lw $8,0($9), Load $8 with the word @mem[$9] */
+ MIPS32_SW(8,0,11), /* sw $8,0($11) */
MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */
MIPS32_ADDI(9,9,4), /* $1+=4 */
return retval;
}
+int mips32_pracc_read_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf)
+{
+ u32 code[] = {
+ /* start: */
+ MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
+ MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
+ MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
+ MIPS32_SW(8,0,15), /* sw $8,($15) */
+ MIPS32_SW(9,0,15), /* sw $9,($15) */
+
+ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
+ MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)),
+ MIPS32_LW(8,0,8), /* $8=mem[$8]; read addr */
+ MIPS32_LUI(9,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $9=MIPS32_PRACC_PARAM_OUT */
+ MIPS32_ORI(9,9,LOWER16(MIPS32_PRACC_PARAM_OUT)),
+
+ MIPS32_LW(8,0,8), /* lw $8,0($8), Load $8 with the word @mem[$8] */
+ MIPS32_SW(8,0,9), /* sw $8,0($9) */
+
+ MIPS32_LW(9,0,15), /* lw $9,($15) */
+ MIPS32_LW(8,0,15), /* lw $8,($15) */
+ MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
+ MIPS32_NOP,
+ MIPS32_B(NEG16(17)), /* b start */
+ MIPS32_NOP,
+ };
+
+ int retval = ERROR_OK;
+ u32 param_in[1];
+
+ param_in[0] = addr;
+
+ if ((retval = mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code,
+ sizeof(param_in)/sizeof(param_in[0]), param_in, sizeof(u32), buf, 1)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ return retval;
+}
+
int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
{
u32 code[] = {
MIPS32_BEQ(0,10,9), /* beq 0, $10, end */
MIPS32_NOP,
- MIPS32_LHU(12,0,9), /* lw $12,0($9), Load $12 with the halfword @mem[$9] */
- MIPS32_SW(12,0,11), /* sw $12,0($11) */
+ MIPS32_LHU(8,0,9), /* lw $8,0($9), Load $8 with the halfword @mem[$9] */
+ MIPS32_SW(8,0,11), /* sw $8,0($11) */
MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */
MIPS32_ADDI(9,9,2), /* $9+=2 */
MIPS32_BEQ(0,10,9), /* beq 0, $10, end */
MIPS32_NOP,
- MIPS32_LBU(12,0,9), /* lw $12,0($9), Load t4 with the byte @mem[t1] */
- MIPS32_SW(12,0,11), /* sw $12,0($11) */
+ MIPS32_LBU(8,0,9), /* lw $8,0($9), Load t4 with the byte @mem[t1] */
+ MIPS32_SW(8,0,11), /* sw $8,0($11) */
MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */
MIPS32_ADDI(9,9,1), /* $9+=1 */
case 2:
return mips32_pracc_write_mem16(ejtag_info, addr, count,(u16*)buf);
case 4:
- return mips32_pracc_write_mem32(ejtag_info, addr, count, (u32*)buf);
+ if(count==1)
+ return mips32_pracc_write_u32(ejtag_info, addr, (u32*)buf);
+ else
+ return mips32_pracc_write_mem32(ejtag_info, addr, count, (u32*)buf);
}
return ERROR_OK;
return ERROR_OK;
}
+int mips32_pracc_write_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf)
+{
+ u32 code[] = {
+ /* start: */
+ MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
+ MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
+ MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
+ MIPS32_SW(8,0,15), /* sw $8,($15) */
+ MIPS32_SW(9,0,15), /* sw $9,($15) */
+
+ MIPS32_LUI(8,UPPER16((MIPS32_PRACC_PARAM_IN+4))), /* $8 = MIPS32_PRACC_PARAM_IN+4 */
+ MIPS32_ORI(8,8,LOWER16((MIPS32_PRACC_PARAM_IN+4))),
+ MIPS32_LW(9,NEG16(4),8), /* Load write addr to $9 */
+
+ MIPS32_LW(8,0,8), /* lw $8,0($8), Load $8 with the word @mem[$8] */
+ MIPS32_SW(8,0,9), /* sw $8,0($9) */
+
+ MIPS32_LW(9,0,15), /* lw $9,($15) */
+ MIPS32_LW(8,0,15), /* lw $8,($15) */
+ MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
+ MIPS32_NOP,
+ MIPS32_B(NEG16(15)), /* b start */
+ MIPS32_NOP,
+ };
+
+ /* TODO remove array */
+ u32 param_in[1+1];
+ param_in[0] = addr;
+ param_in[1] = *buf;
+
+ mips32_pracc_exec(ejtag_info, sizeof(code)/sizeof(code[0]), code, \
+ sizeof(param_in)/sizeof(param_in[0]),param_in, 0, NULL, 1);
+
+ return ERROR_OK;
+}
+
int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
{
u32 code[] = {
extern int mips32_pracc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
extern int mips32_pracc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
extern int mips32_pracc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
+extern int mips32_pracc_read_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf);
extern int mips32_pracc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf);
extern int mips32_pracc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf);
extern int mips32_pracc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf);
+extern int mips32_pracc_write_u32(mips_ejtag_t *ejtag_info, u32 addr, u32 *buf);
extern int mips32_pracc_read_regs(mips_ejtag_t *ejtag_info, u32 *regs);
extern int mips32_pracc_write_regs(mips_ejtag_t *ejtag_info, u32 *regs);
Code Review / openocd.git / commitdiff