As exposed by arm-none-eabi build, fix the wrong modifiers.
Change-Id: Ia6ce7c5c1d40e95059525c3e5d81b752df2fea7c
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2122
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
#define SAM4L_NUM_SECTORS 16
/* Locations in memory map */
#define SAM4L_NUM_SECTORS 16
/* Locations in memory map */
-#define SAM4L_FLASH 0x00000000 /* Flash region */
+#define SAM4L_FLASH ((uint32_t)0x00000000) /* Flash region */
#define SAM4L_FLASH_USER 0x00800000 /* Flash user page region */
#define SAM4L_FLASHCALW 0x400A0000 /* Flash controller */
#define SAM4L_CHIPID 0x400E0740 /* Chip Identification */
#define SAM4L_FLASH_USER 0x00800000 /* Flash user page region */
#define SAM4L_FLASHCALW 0x400A0000 /* Flash controller */
#define SAM4L_CHIPID 0x400E0740 /* Chip Identification */
/* Issue a quick page read to verify that we've erased this page */
res = sam4l_flash_command(bank->target, SAM4L_FCMD_QPR, pn);
if (res != ERROR_OK) {
/* Issue a quick page read to verify that we've erased this page */
res = sam4l_flash_command(bank->target, SAM4L_FCMD_QPR, pn);
if (res != ERROR_OK) {
- LOG_ERROR("Quick page read %d failed", pn);
+ LOG_ERROR("Quick page read %" PRIu32 " failed", pn);
chip->flash_kb = 512;
break;
default:
chip->flash_kb = 512;
break;
default:
- LOG_ERROR("Unknown flash size (chip ID is %08X), assuming 128K", id);
+ LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32 "), assuming 128K", id);
chip->flash_kb = 128;
break;
}
chip->flash_kb = 128;
break;
}
/* Done */
chip->probed = true;
/* Done */
chip->probed = true;
- LOG_INFO("SAM4L MCU: %s (Rev %c) (%uKB Flash with %d %dB pages, %uKB RAM)",
- chip->details ? chip->details->name : "unknown", 'A' + (id & 0xF),
+ LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32 "KB Flash with %d %" PRId32 "B pages, %" PRIu32 "KB RAM)",
+ chip->details ? chip->details->name : "unknown", (char)('A' + (id & 0xF)),
chip->flash_kb, chip->num_pages, chip->page_size, chip->ram_kb);
return ERROR_OK;
chip->flash_kb, chip->num_pages, chip->page_size, chip->ram_kb);
return ERROR_OK;
#define SAMD_NUM_SECTORS 16
#define SAMD_NUM_SECTORS 16
-#define SAMD_FLASH 0x00000000 /* physical Flash memory */
+#define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
#define SAMD_DSU 0x41002000 /* Device Service Unit */
#define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
#define SAMD_DSU 0x41002000 /* Device Service Unit */
#define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
* multiplied by the number of pages. */
if (bank->size != chip->num_pages * chip->page_size) {
LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
* multiplied by the number of pages. */
if (bank->size != chip->num_pages * chip->page_size) {
LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
- "Identified %uKB Flash but NVMCTRL reports %u %uB pages",
+ "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
part->flash_kb, chip->num_pages, chip->page_size);
}
part->flash_kb, chip->num_pages, chip->page_size);
}
/* Done */
chip->probed = true;
/* Done */
chip->probed = true;
- LOG_INFO("SAMD MCU: %s (%uKB Flash, %uKB RAM)", part->name,
+ LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
part->flash_kb, part->ram_kb);
return ERROR_OK;
part->flash_kb, part->ram_kb);
return ERROR_OK;
}
if (res != ERROR_OK || error) {
}
if (res != ERROR_OK || error) {
- LOG_ERROR("Failed to erase row containing %08X" PRIx32, address);
+ LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
"start address 0x%" PRIx32, component_base,
/* component may take multiple 4K pages */
(uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
"start address 0x%" PRIx32, component_base,
/* component may take multiple 4K pages */
(uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
- command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
- (c_cid1 >> 4) & 0xf,
+ command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
+ (uint8_t)((c_cid1 >> 4) & 0xf),
/* See ARM IHI 0029B Table 3-3 */
class_description[(c_cid1 >> 4) & 0xf]);
/* See ARM IHI 0029B Table 3-3 */
class_description[(c_cid1 >> 4) & 0xf]);
- command_print(cmd_ctx, "\t\tType is 0x%02x, %s, %s",
- devtype & 0xff,
+ command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
+ (uint8_t)(devtype & 0xff),
major, subtype);
/* REVISIT also show 0xfc8 DevId */
}
major, subtype);
/* REVISIT also show 0xfc8 DevId */
}
read_buf[i] = read_ref[i];
}
command_print_sameline(CMD_CTX,
read_buf[i] = read_ref[i];
}
command_print_sameline(CMD_CTX,
- "Test read %d x %d @ %d to %saligned buffer: ", count,
+ "Test read %" PRIu32 " x %d @ %d to %saligned buffer: ", count,
size, offset, host_offset ? "un" : "");
struct duration bench;
size, offset, host_offset ? "un" : "");
struct duration bench;
for (size_t i = 0; i < host_bufsiz; i++)
write_buf[i] = rand();
command_print_sameline(CMD_CTX,
for (size_t i = 0; i < host_bufsiz; i++)
write_buf[i] = rand();
command_print_sameline(CMD_CTX,
- "Test write %d x %d @ %d from %saligned buffer: ", count,
+ "Test write %" PRIu32 " x %d @ %d from %saligned buffer: ", count,
size, offset, host_offset ? "un" : "");
retval = target_write_memory(target, wa->address, 1, num_bytes, test_pattern);
size, offset, host_offset ? "un" : "");
retval = target_write_memory(target, wa->address, 1, num_bytes, test_pattern);
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