convert your scripts to the new names, since those procedures
will not be around forever.
jtag_khz ... is now adapter_khz
+ jtag_nsrst_delay ... is now adapter_nsrst_delay
Boundary Scan:
requirements that all reset pulses last for at least a
certain amount of time; and reset buttons commonly have
hardware debouncing.
-Use the @command{jtag_nsrst_delay} and @command{jtag_ntrst_delay}
+Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
commands to say when extra delays are needed.
@item @emph{Drive type} ... Reset lines often have a pullup
allowing it to be deasserted.
@end deffn
-@deffn {Command} jtag_nsrst_delay milliseconds
+@deffn {Command} adapter_nsrst_delay milliseconds
How long (in milliseconds) OpenOCD should wait after deasserting
nSRST (active-low system reset) before starting new JTAG operations.
When a board has a reset button connected to SRST line it will
static int jtag_verify = 1;
/* how long the OpenOCD should wait before attempting JTAG communication after reset lines deasserted (in ms) */
-static int jtag_nsrst_delay = 0; /* default to no nSRST delay */
+static int adapter_nsrst_delay = 0; /* default to no nSRST delay */
static int jtag_ntrst_delay = 0; /* default to no nTRST delay */
static int jtag_nsrst_assert_width = 0; /* width of assertion */
static int jtag_ntrst_assert_width = 0; /* width of assertion */
}
else {
LOG_DEBUG("SRST line released");
- if (jtag_nsrst_delay)
- jtag_add_sleep(jtag_nsrst_delay * 1000);
+ if (adapter_nsrst_delay)
+ jtag_add_sleep(adapter_nsrst_delay * 1000);
}
}
void jtag_set_nsrst_delay(unsigned delay)
{
- jtag_nsrst_delay = delay;
+ adapter_nsrst_delay = delay;
}
unsigned jtag_get_nsrst_delay(void)
{
- return jtag_nsrst_delay;
+ return adapter_nsrst_delay;
}
void jtag_set_ntrst_delay(unsigned delay)
{
# FIXME phase these aids out after about April 2011
#
proc jtag_khz args { eval adapter_khz $args }
+proc jtag_nsrst_delay args { eval adapter_nsrst_delay $args }
# END MIGRATION AIDS
return ERROR_OK;
}
-COMMAND_HANDLER(handle_jtag_nsrst_delay_command)
+COMMAND_HANDLER(handle_adapter_nsrst_delay_command)
{
if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
jtag_set_nsrst_delay(delay);
}
- command_print(CMD_CTX, "jtag_nsrst_delay: %u", jtag_get_nsrst_delay());
+ command_print(CMD_CTX, "adapter_nsrst_delay: %u", jtag_get_nsrst_delay());
return ERROR_OK;
}
"With or without argument, display current setting.",
.usage = "[khz]",
},
+ {
+ .name = "adapter_nsrst_delay",
+ .handler = handle_adapter_nsrst_delay_command,
+ .mode = COMMAND_ANY,
+ .help = "delay after deasserting srst in ms",
+ .usage = "[milliseconds]",
+ },
{
.name = "interface",
.handler = handle_interface_command,
"[trst_push_pull|trst_open_drain] "
"[srst_push_pull|srst_open_drain]",
},
- {
- .name = "jtag_nsrst_delay",
- .handler = handle_jtag_nsrst_delay_command,
- .mode = COMMAND_ANY,
- .help = "delay after deasserting srst in ms",
- .usage = "[milliseconds]",
- },
{
.name = "jtag_ntrst_delay",
.handler = handle_jtag_ntrst_delay_command,
# affected by the board and type of JTAG adapter. A value of 200 ms seems
# to work reliably for the configuration listed in the file header above.
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
source [find target/pxa270.cfg]
# longer-than-normal reset delay
-jtag_nsrst_delay 800
+adapter_nsrst_delay 800
reset_config trst_and_srst separate
# Determined by trial and error
reset_config trst_and_srst combined
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 0
# jtag speed
adapter_khz 3000
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
#LM3S1968 Evaluation Board has only srst
reset_config srst_only
# jtag speed
adapter_khz 500
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
#LM3S811 Evaluation Board has only srst
reset_config srst_only
# jtag speed
adapter_khz 500
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
#LM3S9B9x Evaluation Board has only srst
reset_config srst_only
# Micrel MIC2775-29YM5 Supervisor
# Reset output will remain active for 280ms (maximum)
#
-jtag_nsrst_delay 300
+adapter_nsrst_delay 300
jtag_ntrst_delay 300
# http://www.hitex.com/
# Delays on reset lines
-jtag_nsrst_delay 50
+adapter_nsrst_delay 50
jtag_ntrst_delay 1
# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# set jtag speed
adapter_khz 3000
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
source [find target/pxa255.cfg]
-jtag_nsrst_delay 250
+adapter_nsrst_delay 250
jtag_ntrst_delay 250
# NOTE: until after pinmux and such are set up, only CS0 is
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
nand device s3c2440 0
- jtag_nsrst_delay 100
+ adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
init
source [find target/lpc3250.cfg]
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 1
adapter_khz 200
reset_config trst_and_srst separate
reset_config trst_and_srst
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
#xscale debug_handler 0 0xFFFF0800 # debug handler base address
jtag_nsrst_assert_width 100
jtag_ntrst_assert_width 100
# don't talk to JTAG after reset for: [ms]
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg.
#
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
set _CPUTAPID 0x3f0f0f0f
}
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
## JTAG scan chain
# Atheros AR71xx MIPS 24Kc SoC.
# tested on PB44 refererence board
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
#
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-jtag_nsrst_delay 300
+adapter_nsrst_delay 300
jtag_ntrst_delay 200
jtag_rclk 3
reset_config trst_and_srst
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
#
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-jtag_nsrst_delay 300
+adapter_nsrst_delay 300
jtag_ntrst_delay 200
jtag_rclk 3
target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
reset_config trst_and_srst srst_gates_jtag
-jtag_nsrst_delay 5
+adapter_nsrst_delay 5
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# jtag speed
adapter_khz 500
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#LM3S6965 Evaluation Board has only srst
}
#delays on reset lines
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
# LPC2000 & LPC1700 -> SRST causes TRST
reset_config trst_and_srst srst_pulls_trst
# reset delays
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
reset_config trst_and_srst srst_pulls_trst
# reset delays
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
adapter_khz 1000
reset_config trst_and_srst srst_pulls_trst
# reset delays
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
set _CPUTAPID 0x4f1f0f0f
}
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate
set _CPUTAPID 0xffffffff
}
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
#use combined on interfaces or targets that can't set TRST/SRST separately
}
#delays on reset lines
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
# LPC2000 -> SRST causes TRST
}
#delays on reset lines
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
# LPC2000 -> SRST causes TRST
adapter_khz 4500
reset_config srst_only
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
#jtag scan chain
if { [info exists CPUTAPID ] } {
# FIXME most reset config belongs in board code
reset_config trst_and_srst
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
# jtag scan chain
set _CPUTAPID 0x0692602f
}
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
# its standalone siblings (like TMS320VC5502) of the same era
}
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
}
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# set adapter_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 260
+adapter_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 250
set _CPUTAPID_PXA32X_C0 0x7E642013
}
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# set adapter_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 260
+adapter_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm1176
-jtag_nsrst_delay 500
+adapter_nsrst_delay 500
jtag_ntrst_delay 500
#reset configuration
set _CPUTAPID 0x08630001
}
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter_khz 1000
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
-jtag_nsrst_delay 500
+adapter_nsrst_delay 500
jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
-jtag_nsrst_delay 500
+adapter_nsrst_delay 500
jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
# jtag speed. We need to stick to 16kHz until we've finished reset.
jtag_rclk 16
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
jtag_nsrst_assert_width 100
jtag_ntrst_assert_width 100
# don't talk to JTAG after reset for: [ms]
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-jtag_nsrst_delay 20
+adapter_nsrst_delay 20
jtag_ntrst_delay 20
######################
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-jtag_nsrst_delay 20
+adapter_nsrst_delay 20
jtag_ntrst_delay 20
######################
reset_config trst_and_srst separate
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
-jtag_nsrst_delay 200
+adapter_nsrst_delay 200
jtag_ntrst_delay 200
#use combined on interfaces or targets that can't set TRST/SRST separately
Code Review / openocd.git / commitdiff