-enum nrf51_ficr_registers {
- NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
-
-#define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
-
- NRF51_FICR_CODEPAGESIZE = NRF51_FICR_REG(0x010),
- NRF51_FICR_CODESIZE = NRF51_FICR_REG(0x014),
- NRF51_FICR_CLENR0 = NRF51_FICR_REG(0x028),
- NRF51_FICR_PPFC = NRF51_FICR_REG(0x02C),
- NRF51_FICR_NUMRAMBLOCK = NRF51_FICR_REG(0x034),
- NRF51_FICR_SIZERAMBLOCK0 = NRF51_FICR_REG(0x038),
- NRF51_FICR_SIZERAMBLOCK1 = NRF51_FICR_REG(0x03C),
- NRF51_FICR_SIZERAMBLOCK2 = NRF51_FICR_REG(0x040),
- NRF51_FICR_SIZERAMBLOCK3 = NRF51_FICR_REG(0x044),
- NRF51_FICR_CONFIGID = NRF51_FICR_REG(0x05C),
- NRF51_FICR_DEVICEID0 = NRF51_FICR_REG(0x060),
- NRF51_FICR_DEVICEID1 = NRF51_FICR_REG(0x064),
- NRF51_FICR_ER0 = NRF51_FICR_REG(0x080),
- NRF51_FICR_ER1 = NRF51_FICR_REG(0x084),
- NRF51_FICR_ER2 = NRF51_FICR_REG(0x088),
- NRF51_FICR_ER3 = NRF51_FICR_REG(0x08C),
- NRF51_FICR_IR0 = NRF51_FICR_REG(0x090),
- NRF51_FICR_IR1 = NRF51_FICR_REG(0x094),
- NRF51_FICR_IR2 = NRF51_FICR_REG(0x098),
- NRF51_FICR_IR3 = NRF51_FICR_REG(0x09C),
- NRF51_FICR_DEVICEADDRTYPE = NRF51_FICR_REG(0x0A0),
- NRF51_FICR_DEVICEADDR0 = NRF51_FICR_REG(0x0A4),
- NRF51_FICR_DEVICEADDR1 = NRF51_FICR_REG(0x0A8),
- NRF51_FICR_OVERRIDEN = NRF51_FICR_REG(0x0AC),
- NRF51_FICR_NRF_1MBIT0 = NRF51_FICR_REG(0x0B0),
- NRF51_FICR_NRF_1MBIT1 = NRF51_FICR_REG(0x0B4),
- NRF51_FICR_NRF_1MBIT2 = NRF51_FICR_REG(0x0B8),
- NRF51_FICR_NRF_1MBIT3 = NRF51_FICR_REG(0x0BC),
- NRF51_FICR_NRF_1MBIT4 = NRF51_FICR_REG(0x0C0),
- NRF51_FICR_BLE_1MBIT0 = NRF51_FICR_REG(0x0EC),
- NRF51_FICR_BLE_1MBIT1 = NRF51_FICR_REG(0x0F0),
- NRF51_FICR_BLE_1MBIT2 = NRF51_FICR_REG(0x0F4),
- NRF51_FICR_BLE_1MBIT3 = NRF51_FICR_REG(0x0F8),
- NRF51_FICR_BLE_1MBIT4 = NRF51_FICR_REG(0x0FC),
+enum nrf5_ficr_registers {
+ NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
+
+#define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
+
+ NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
+ NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
+ NRF5_FICR_CLENR0 = NRF5_FICR_REG(0x028),
+ NRF5_FICR_PPFC = NRF5_FICR_REG(0x02C),
+ NRF5_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
+ NRF5_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
+ NRF5_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
+ NRF5_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
+ NRF5_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
+ NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
+ NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
+ NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
+ NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
+ NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
+ NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
+ NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
+ NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
+ NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
+ NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
+ NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
+ NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
+ NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
+ NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
+ NRF5_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
+ NRF5_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
+ NRF5_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
+ NRF5_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
+ NRF5_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
+ NRF5_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
+ NRF5_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
+ NRF5_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
+ NRF5_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
+ NRF5_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
+ NRF5_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),