Modify the format strings to properly handle uint32_t data types.
Change the type of variable retval in 'nor/ambiqmicro.c' to match
both the value to carry and the returned type of the function.
Fix the prototype mismatch of function lpc2900_address2sector()
between the header and the C file.
Change-Id: I68ffba9bd83eec8132f83bff3af993861fd09d84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5816
Tested-by: jenkins
static const char target_not_halted_err_msg[] =
"target must be halted to use mx3 NAND flash controller";
static const char data_block_size_err_msg[] =
- "minimal granularity is one half-word, %" PRId32 " is incorrect";
+ "minimal granularity is one half-word, %" PRIu32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] =
"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
static const char target_not_halted_err_msg[] =
"target must be halted to use mxc NAND flash controller";
static const char data_block_size_err_msg[] =
- "minimal granularity is one half-word, %" PRId32 " is incorrect";
+ "minimal granularity is one half-word, %" PRIu32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] =
"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
bad_state = " (block condition unknown)";
command_print(CMD,
- "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
+ "\t#%i: 0x%8.8" PRIx32 " (%" PRIu32 "kB) %s%s",
j,
p->blocks[j].offset,
p->blocks[j].size / 1024,
res = buf_get_u32(reg_params[4].value, 0, 32);
if (res) {
- LOG_ERROR("aducm360 fast sync algorithm reports an error (%02X)", res);
+ LOG_ERROR("aducm360 fast sync algorithm reports an error (%02" PRIX32 ")", res);
retval = ERROR_FAIL;
break;
}
} else {
res = buf_get_u32(reg_params[4].value, 0, 32); /*RESULT*/
if (res) {
- LOG_ERROR("aducm360 fast async algorithm reports an error (%02X)", res);
+ LOG_ERROR("aducm360 fast async algorithm reports an error (%02" PRIX32 ")", res);
retval = ERROR_FAIL;
}
}
/* Set PartNum to default device */
PartNum = 0;
}
- LOG_DEBUG("Part number: 0x%x", PartNum);
+ LOG_DEBUG("Part number: 0x%" PRIx32, PartNum);
/*
* Determine device class.
ambiqmicro_info->target_name =
ambiqmicroParts[0].partname;
- LOG_DEBUG("num_pages: %d, pagesize: %d, flash: %d, sram: %d",
+ LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
ambiqmicro_info->num_pages,
ambiqmicro_info->pagesize,
ambiqmicro_info->flshsiz,
}
/* target flash failed, unknown cause. */
if (retflash != 0) {
- LOG_ERROR("Flash not happy: status(0x%x)", retflash);
+ LOG_ERROR("Flash not happy: status(0x%" PRIx32 ")", retflash);
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
struct target *target = bank->target;
- uint32_t retval = ERROR_OK;
+ int retval;
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
break;
}
- LOG_DEBUG("address = 0x%08x", address);
+ LOG_DEBUG("address = 0x%08" PRIx32, address);
retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
- uint32_t retval;
+ int retval;
/* try using a block write */
retval = ambiqmicro_write_block(bank, buffer, offset, count);
static int ambiqmicro_probe(struct flash_bank *bank)
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
- uint32_t retval;
+ int retval;
/* If this is a ambiqmicro chip, it has flash; probe() is just
* to figure out how much is present. Only do it once.
{
struct target *target = NULL;
struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
- uint32_t retval = ERROR_OK;
+ int retval;
ambiqmicro_info = bank->driver_priv;
target = bank->target;
/*
* Program OTP.
*/
- LOG_INFO("Programming OTP offset 0x%08x", offset);
+ LOG_INFO("Programming OTP offset 0x%08" PRIx32, offset);
/*
* passed pc, addr = ROM function, handle breakpoints, not debugging.
return ERROR_COMMAND_SYNTAX_ERROR;
struct flash_bank *bank;
- uint32_t retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
{
struct flash_bank *bank;
uint32_t first, last;
- uint32_t retval;
+ int retval;
if (CMD_ARGC < 3)
return ERROR_COMMAND_SYNTAX_ERROR;
{
struct flash_bank *bank;
uint32_t offset, count;
- uint32_t retval;
+ int retval;
if (CMD_ARGC < 3)
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
- command_print(CMD, "offset=0x%08x count=%d", offset, count);
+ command_print(CMD, "offset=0x%08" PRIx32 " count=%" PRIu32, offset, count);
CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
}
/* show the basics */
- LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
+ LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
REG_NAME_WIDTH, regname,
dwidth, v,
hwidth, v);
sam4_explain_chipid_cidr(pPrivate->pChip);
return ERROR_FAIL;
} else {
- LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08x", pDetails->name, pDetails->chipid_cidr);
+ LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, pDetails->name, pDetails->chipid_cidr);
}
/* DANGER: THERE ARE DRAGONS HERE */
/* Done */
chip->probed = true;
- LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32 "KB Flash with %d %" PRId32 "B pages, %" PRIu32 "KB RAM)",
+ LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32 "KB Flash with %d %" PRIu32 "B pages, %" PRIu32 "KB RAM)",
chip->details ? chip->details->name : "unknown", (char)('A' + (id & 0xF)),
chip->flash_kb, chip->num_pages, chip->page_size, chip->ram_kb);
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
- LOG_DEBUG("Write flash bank:%u page number:%" PRIi32 "", bank->bank_number, pagen);
+ LOG_DEBUG("Write flash bank:%u page number:%" PRIu32, bank->bank_number, pagen);
}
return ERROR_OK;
*transferred = 0;
pracc_queue_init(&ctx);
- LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
+ LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08" PRIx32 ", %p, %d)",
target, ath79_info->io_base, data, len);
LOG_DEBUG("max code %d => max len %d. to_xfer %d",
ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
if (address & 0xff) {
- LOG_ERROR("ath79_write_page: unaligned write address: %08x",
+ LOG_ERROR("ath79_write_page: unaligned write address: %08" PRIx32,
address);
return ERROR_FAIL;
}
return ERROR_FAIL;
}
if (len > ath79_info->dev->pagesize) {
- LOG_ERROR("ath79_write_page: len bigger than page size %d: %d",
+ LOG_ERROR("ath79_write_page: len bigger than page size %" PRIu32 ": %" PRIu32,
pagesize, len);
return ERROR_FAIL;
}
if (i == len) /* all 0xff, no need to program. */
return ERROR_OK;
- LOG_INFO("writing %d bytes to flash page @0x%08x", len, address);
+ LOG_INFO("writing %" PRIu32 " bytes to flash page @0x%08" PRIx32, len, address);
memcpy(ath79_info->spi.page_buf, buffer, len);
__func__, address, len);
if (address & 0xff) {
- LOG_ERROR("ath79_read_buffer: unaligned read address: %08x",
+ LOG_ERROR("ath79_read_buffer: unaligned read address: %08" PRIx32,
address);
return ERROR_FAIL;
}
- LOG_INFO("reading %d bytes from flash @0x%08x", len, address);
+ LOG_INFO("reading %" PRIu32 " bytes from flash @0x%08" PRIx32, len, address);
/* bitbang command */
ath79_spi_bitbang_prepare(bank);
{
if (bank->base != SAMD_FLASH) {
LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try "
- "0x%08" PRIx32 "[same5] )", bank->base, SAMD_FLASH);
+ "0x%08x[same5] )", bank->base, SAMD_FLASH);
return ERROR_FAIL;
}
if (ERROR_OK != r)
return r;
}
- snprintf(buf, buf_size, "Cortex-M7 detected with %d kB flash",
+ snprintf(buf, buf_size, "Cortex-M7 detected with %" PRIu32 " kB flash",
bank->size / 1024);
return ERROR_OK;
}
return ERROR_COMMAND_SYNTAX_ERROR;
}
- uint32_t v;
+ unsigned v;
if (!strcmp("show", CMD_ARGV[0])) {
if (who == -1) {
showall:
}
LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
- LOG_DEBUG("count is %" PRId32 "", count);
+ LOG_DEBUG("count is %" PRIu32 "", count);
if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
return ERROR_FAIL;
command = FLASH_CMD_ERASE_PAGE;
for (unsigned int i = first; i <= last; i++) {
address = bank->base+i*FLASH_PAGE_SIZE(bluenrgx_info);
- LOG_DEBUG("address = %08x, index = %u", address, i);
+ LOG_DEBUG("address = %08" PRIx32 ", index = %u", address, i);
if (bluenrgx_write_flash_reg(bank, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FLASH_BANK_NOT_PROBED;
if ((offset + count) > bank->size) {
- LOG_ERROR("Requested write past beyond of flash size: (offset+count) = %d, size=%d",
+ LOG_ERROR("Requested write past beyond of flash size: (offset+count) = %" PRIu32 ", size=%" PRIu32,
(offset + count),
bank->size);
return ERROR_FLASH_DST_OUT_OF_BANK;
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
- LOG_DEBUG("address = %08x", address);
- LOG_DEBUG("count = %08x", count);
+ LOG_DEBUG("address = %08" PRIx32, address);
+ LOG_DEBUG("count = %08" PRIx32, count);
retval = target_run_flash_async_algorithm(target,
buffer,
}
printed = snprintf(buf, buf_size,
- "%s device: ICEPick ID 0x%08x, USER ID 0x%08x\n",
+ "%s device: ICEPick ID 0x%08" PRIx32 ", USER ID 0x%08" PRIx32 "\n",
device, cc26xx_bank->icepick_id, cc26xx_bank->user_id);
if (printed >= buf_size)
/* Check for valid size */
if (wordcount > bufferwsize) {
- LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
+ LOG_ERROR("Number of data words %" PRIu32 " exceeds available buffersize %" PRIu32,
wordcount, buffersize);
return ERROR_FLASH_OPERATION_FAILED;
}
/* Check for valid size */
if (wordcount > bufferwsize) {
- LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
- PRId32, wordcount, buffersize);
+ LOG_ERROR("Number of data words %" PRIu32 " exceeds available buffersize %"
+ PRIu32, wordcount, buffersize);
return ERROR_FLASH_OPERATION_FAILED;
}
/* handle unaligned tail bytes */
if (count > 0) {
- LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
+ LOG_INFO("Fixup %" PRIu32 " unaligned tail bytes", count);
/* read a complete word from flash */
retval = cfi_target_read_memory(bank, write_p, 1, current_word);
LOG_WARNING("Section start address " TARGET_ADDR_FMT
" breaks the required alignment of flash bank %s",
run_address, c->name);
- LOG_WARNING("Padding %d bytes from " TARGET_ADDR_FMT,
+ LOG_WARNING("Padding %" PRIu32 " bytes from " TARGET_ADDR_FMT,
padding_at_start, aligned_start);
run_address -= padding_at_start;
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
snprintf(buf, buf_size,
- "%4s cfg at 0x%" PRIx32 ", clock %" PRId32 ", wait_states %" PRId32,
+ "%4s cfg at 0x%" PRIx32 ", clock %" PRIu32 ", wait_states %" PRIu32,
"", /* align with first line */
esirisc_info->cfg,
esirisc_info->clock,
int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
- LOG_ERROR("fespi_write_reg() error writing 0x%x to " TARGET_ADDR_FMT,
+ LOG_ERROR("fespi_write_reg() error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT,
value, fespi_info->ctrl_base + address);
return result;
}
break;
int64_t now = timeval_ms();
if (now - start > 1000) {
- LOG_ERROR("rxfifo didn't go positive (value=0x%x).", value);
+ LOG_ERROR("rxfifo didn't go positive (value=0x%" PRIx32 ").", value);
return ERROR_TARGET_TIMEOUT;
}
}
uint32_t ii;
if (offset & 0xFF000000) {
- LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x",
+ LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%" PRIx32,
offset);
return ERROR_FAIL;
}
const uint8_t *buffer, uint32_t chip_offset, uint32_t len)
{
if (chip_offset & 0xFF000000) {
- LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x",
+ LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%" PRIx32,
chip_offset);
return ERROR_FAIL;
}
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run_ret;
} else if (result != 0) {
- LOG_ERROR("Unexpected error %d from flash sector erase programming algorithm", result);
+ LOG_ERROR("Unexpected error %" PRIu32 " from flash sector erase programming algorithm", result);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run_ret;
} else
#include "../../../contrib/loaders/flash/fm4/write.inc"
};
- LOG_DEBUG("Spansion FM4 write at 0x%08" PRIx32 " (%" PRId32 " bytes)",
+ LOG_DEBUG("Spansion FM4 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
offset, byte_count);
if (offset & 0x1) {
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
if (byte_count & 0x1) {
- LOG_WARNING("length %" PRId32 " is not 2-byte aligned, rounding up",
+ LOG_WARNING("length %" PRIu32 " is not 2-byte aligned, rounding up",
byte_count);
}
uint32_t halfwords = MIN(halfword_count, data_workarea->size / 2);
uint32_t addr = bank->base + offset;
- LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
+ LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(halfwords * 2, byte_count), data_workarea->address);
retval = target_write_buffer(target, data_workarea->address,
goto err_write_data;
}
- LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRId32 "x)",
+ LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
addr, addr + halfwords * 2 - 1, halfwords);
buf_set_u32(reg_params[0].value, 0, 32, (addr & ~0xffff) | 0xAA8);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run_ret;
} else if (result != 0) {
- LOG_ERROR("Unexpected error %d from flash write "
+ LOG_ERROR("Unexpected error %" PRIu32 " from flash write "
"programming algorithm", result);
retval = ERROR_FLASH_OPERATION_FAILED;
goto err_run_ret;
else
k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
if (k_chip->pflash_size != 2048<<10)
- LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
+ LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %" PRIu32 " KB", k_chip->pflash_size>>10);
break;
default:
k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
size_k = bank->size / 1024;
- LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
+ LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
} else if (k_bank->bank_number < num_blocks) {
}
size_k = bank->size / 1024;
- LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
+ LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
} else {
{
struct lpc2000_flash_bank *lpc2000_info = bank->driver_priv;
- snprintf(buf, buf_size, "lpc2000 flash driver variant: %i, clk: %" PRIi32 "kHz", lpc2000_info->variant,
+ snprintf(buf, buf_size, "lpc2000 flash driver variant: %i, clk: %" PRIu32 "kHz", lpc2000_info->variant,
lpc2000_info->cclk);
return ERROR_OK;
static uint32_t lpc2900_run_bist128(struct flash_bank *bank,
uint32_t addr_from, uint32_t addr_to,
uint32_t signature[4]);
-static uint32_t lpc2900_address2sector(struct flash_bank *bank, uint32_t offset);
+static unsigned int lpc2900_address2sector(struct flash_bank *bank, uint32_t offset);
static uint32_t lpc2900_calc_tr(uint32_t clock_var, uint32_t time_var);
/*********************** Helper functions **************************/
unsigned int flc_base;
unsigned int sector_size;
unsigned int clkdiv_value;
- unsigned int int_state;
+ uint32_t int_state;
unsigned int burst_size_bits;
};
}
info = calloc(sizeof(struct max32xxx_flash_bank), 1);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], info->flash_size);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->flc_base);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->sector_size);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], info->clkdiv_value);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], info->flash_size);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], info->flc_base);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], info->sector_size);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], info->clkdiv_value);
if (CMD_ARGC > 9)
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->burst_size_bits);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[9], info->burst_size_bits);
else
info->burst_size_bits = 32;
} while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND));
if (retry <= 0) {
- LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address);
+ LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address);
return ERROR_FLASH_OPERATION_FAILED;
}
while (remaining >= 16) {
if ((address & 0xFFF) == 0)
- LOG_DEBUG("Writing @ 0x%08x", address);
+ LOG_DEBUG("Writing @ 0x%08" PRIx32, address);
target_write_buffer(target, info->flc_base + FLSH_DATA0, 16, buffer);
flsh_cn |= 0x00000001;
} while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND));
if (retry <= 0) {
- LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address);
+ LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address);
return ERROR_FLASH_OPERATION_FAILED;
}
} while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND));
if (retry <= 0) {
- LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address);
+ LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address);
return ERROR_FLASH_OPERATION_FAILED;
}
} while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND));
if (retry <= 0) {
- LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address);
+ LOG_ERROR("Timed out waiting for flash write @ 0x%08" PRIx32, address);
return ERROR_FLASH_OPERATION_FAILED;
}
}
/* Check access violations */
target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int);
if (flsh_int & FLSH_INT_AF) {
- LOG_ERROR("Flash Error writing 0x%x bytes at 0x%08x", count, offset);
+ LOG_ERROR("Flash Error writing 0x%" PRIx32 " bytes at 0x%08" PRIx32, count, offset);
max32xxx_flash_op_post(bank);
return ERROR_FLASH_OPERATION_FAILED;
}
if ((arm_pid == ARM_PID_DEFAULT_CM3) || arm_pid == ARM_PID_DEFAULT_CM4) {
uint32_t max326xx_id;
target_read_u32(target, MAX326XX_ID_REG, &max326xx_id);
- LOG_DEBUG("max326xx_id = 0x%x", max326xx_id);
+ LOG_DEBUG("max326xx_id = 0x%" PRIx32, max326xx_id);
max326xx_id = ((max326xx_id & 0xFF000000) >> 24);
if (max326xx_id == MAX326XX_ID)
info->max326xx = 1;
/* Explicit device type check failed. Report this. */
LOG_WARNING(
"msp432: Unrecognized MSP432P4 Device ID and Hardware "
- "Rev (%04X, %02X)", msp432_bank->device_id,
+ "Rev (%04" PRIX32 ", %02" PRIX32 ")", msp432_bank->device_id,
msp432_bank->hardware_rev);
} else if (MSP432P401X_DEPR == msp432_bank->device_type) {
LOG_WARNING(
/* Explicit device type check failed. Report this. */
LOG_WARNING(
"msp432: Unrecognized MSP432E4 DID0 and DID1 values "
- "(%08X, %08X)", msp432_bank->device_id,
+ "(%08" PRIX32 ", %08" PRIX32 ")", msp432_bank->device_id,
msp432_bank->hardware_rev);
}
break;
case MSP432E4X_GUESS:
printed = snprintf(buf, buf_size,
- "Unrecognized MSP432E4 DID0 and DID1 IDs (%08X, %08X)",
+ "Unrecognized MSP432E4 DID0 and DID1 IDs (%08" PRIX32 ", %08" PRIX32 ")",
msp432_bank->device_id, msp432_bank->hardware_rev);
break;
case MSP432P401X_GUESS:
case MSP432P411X_GUESS:
default:
printed = snprintf(buf, buf_size,
- "Unrecognized MSP432P4 Device ID and Hardware Rev (%04X, %02X)",
+ "Unrecognized MSP432P4 Device ID and Hardware Rev (%04" PRIX32 ", %02" PRIX32 ")",
msp432_bank->device_id, msp432_bank->hardware_rev);
break;
}
else
return ERROR_COMMAND_SYNTAX_ERROR;
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], uflash_addr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], uflash_addr);
retval = target_write_u32(target, UFMA, uflash_addr);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
return retval;
command_print(CMD, "Read userflash %s region:\n"
- "address = 0x%04x,\n"
- "value = 0x%02x.", CMD_ARGV[0], uflash_addr, uflash_data);
+ "address = 0x%04" PRIx32 ",\n"
+ "value = 0x%02" PRIx32 ".", CMD_ARGV[0], uflash_addr, uflash_data);
return retval;
}
else
return ERROR_COMMAND_SYNTAX_ERROR;
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], uflash_addr);
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], uflash_data);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], uflash_addr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], uflash_data);
int page_num = uflash_addr/USERFLASH_PAGE_SIZE;
command_print(CMD, "Write userflash %s region:\n"
- "address = 0x%04x,\n"
- "value = 0x%02x.\n"
+ "address = 0x%04" PRIx32 ",\n"
+ "value = 0x%02" PRIx32 ".\n"
"Please wait ... ", CMD_ARGV[0], uflash_addr, uflash_data);
/* dump */
uint32_t uflash_dump[USERFLASH_PAGE_SIZE];
return ERROR_COMMAND_SYNTAX_ERROR;
uint32_t pin;
- COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], pin);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pin);
if (pin > 15)
return ERROR_COMMAND_SYNTAX_ERROR;
/* write 16 bytes per try */
for (unsigned int i = 0; i < count; i += 16) {
/* current addr */
- LOG_INFO("%d byte of %d", i, count);
+ LOG_INFO("%u byte of %" PRIu32, i, count);
flash_addr = offset + i;
retval = target_write_u32(target, FMA, flash_addr);
if (retval != ERROR_OK)
"\n"
"MEMORY CONFIGURATION\n"
"Bootflash :\n"
- " %d kB total\n"
- " %d pages %d kB each\n"
- " 0x%08x base address\n"
+ " %" PRIu32 " kB total\n"
+ " %" PRIu32 " pages %" PRIu32 " kB each\n"
+ " 0x%08" PRIx32 " base address\n"
"%s"
"Info bootflash :\n"
- " %d kB total\n"
- " %d pages %d kB each\n"
+ " %" PRIu32 " kB total\n"
+ " %" PRIu32 " pages %" PRIu32 " kB each\n"
" %s\n"
"%s"
"Userflash :\n"
- " %d kB total\n"
- " %d pages %d B each\n"
- " %d bit cells\n"
+ " %" PRIu32 " kB total\n"
+ " %" PRIu32 " pages %" PRIu32 " B each\n"
+ " %" PRIu32 " bit cells\n"
" not mapped to global address space\n"
"Info userflash :\n"
- " %d B total\n"
- " %d pages of %d B each\n"
- " %d bit cells\n"
+ " %" PRIu32 " B total\n"
+ " %" PRIu32 " pages of %" PRIu32 " B each\n"
+ " %" PRIu32 " bit cells\n"
" not mapped to global address space\n"
"RAM :\n"
" 192 kB total\n"
" 0x20000000 base address\n"
"External memory :\n"
" 8/16 bit address space\n"
- " 0x%08x base address\n"
+ " 0x%08" PRIx32 " base address\n"
"\n"
"INFOWORD STATUS\n"
"Bootflash info region remap :\n"
"External memory boot port :\n"
" %s\n"
"External memory boot pin :\n"
- " %d\n"
+ " %" PRIu32 "\n"
"External memory interface alternative function :\n"
- " %d\n"
+ " %" PRIu32 "\n"
"Option boot from external memory :\n"
" %s\n",
bflash_size/1024,
/* program command */
for (uint32_t i = 0; i < count; i += 4) {
- LOG_DEBUG("write longword @ %08X", offset + i);
+ LOG_DEBUG("write longword @ %08" PRIX32, offset + i);
retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + offset + i);
if (retval != ERROR_OK)
}
}
- LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
+ LOG_INFO("flash size = %" PRIu32 "kbytes", num_pages / 1024);
free(bank->sectors);
mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
if (timeout-- == 0) {
- LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
+ LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
break;
}
alive_sleep(1);
memset(buf + byte_count, bank->default_padded_value,
EEPROM_ROW_SIZE - byte_count);
- LOG_DEBUG("Padding %d bytes", EEPROM_ROW_SIZE - byte_count);
+ LOG_DEBUG("Padding %" PRIu32 " bytes", EEPROM_ROW_SIZE - byte_count);
retval = psoc5lp_spc_load_row(target, SPC_ARRAY_EEPROM,
buf, EEPROM_ROW_SIZE);
if (retval != ERROR_OK)
bool is_success = (*data_out & SROMAPI_STATUS_MSK) == SROMAPI_STAT_SUCCESS;
if (!is_success) {
- LOG_ERROR("SROM API execution failed. Status: 0x%08X", (uint32_t)*data_out);
+ LOG_ERROR("SROM API execution failed. Status: 0x%08" PRIX32, *data_out);
return ERROR_TARGET_FAILURE;
}
return hr;
snprintf(buf, buf_size,
- "PSoC6 Silicon ID: 0x%08X\n"
+ "PSoC6 Silicon ID: 0x%08" PRIX32 "\n"
"Protection: %s\n"
- "Main Flash size: %d kB\n"
+ "Main Flash size: %" PRIu32 " kB\n"
"Work Flash size: 32 kB\n",
psoc6_info->silicon_id,
protection_to_str(psoc6_info->protection),
{
struct target *target = bank->target;
- LOG_DEBUG("Erasing SECTOR @%08X", addr);
+ LOG_DEBUG("Erasing SECTOR @%08" PRIX32, addr);
int hr = target_write_u32(target, wa->address, SROMAPI_ERASESECTOR_REQ);
if (hr != ERROR_OK)
uint32_t data_out;
hr = call_sromapi(target, SROMAPI_ERASESECTOR_REQ, wa->address, &data_out);
if (hr != ERROR_OK)
- LOG_ERROR("SECTOR @%08X not erased!", addr);
+ LOG_ERROR("SECTOR @%08" PRIX32 " not erased!", addr);
return hr;
}
{
struct target *target = bank->target;
- LOG_DEBUG("Erasing ROW @%08X", addr);
+ LOG_DEBUG("Erasing ROW @%08" PRIX32, addr);
int hr = target_write_u32(target, wa->address, SROMAPI_ERASEROW_REQ);
if (hr != ERROR_OK)
uint32_t data_out;
hr = call_sromapi(target, SROMAPI_ERASEROW_REQ, wa->address, &data_out);
if (hr != ERROR_OK)
- LOG_ERROR("ROW @%08X not erased!", addr);
+ LOG_ERROR("ROW @%08" PRIX32 " not erased!", addr);
return hr;
}
uint32_t data_out;
int hr = ERROR_OK;
- LOG_DEBUG("Programming ROW @%08X", addr);
+ LOG_DEBUG("Programming ROW @%08" PRIX32, addr);
hr = target_alloc_working_area(target, psoc6_info->row_sz + 32, &wa);
if (hr != ERROR_OK)
hr = psoc6_program_row(bank, aligned_addr, page_buf, is_sflash);
if (hr != ERROR_OK) {
- LOG_ERROR("Failed to program Flash at address 0x%08X", aligned_addr);
+ LOG_ERROR("Failed to program Flash at address 0x%08" PRIX32, aligned_addr);
goto exit;
}
* Ignoring return value of mem_ap_write_atomic_u32 seems to be ok here */
if (is_cm0) {
/* Reset the CM0 by asserting SYSRESETREQ. This will also reset CM4 */
- LOG_INFO("psoc6.cm0: bkpt @0x%08X, issuing SYSRESETREQ", reset_addr);
+ LOG_INFO("psoc6.cm0: bkpt @0x%08" PRIX32 ", issuing SYSRESETREQ", reset_addr);
mem_ap_write_atomic_u32(cm->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
} else {
- LOG_INFO("psoc6.cm4: bkpt @0x%08X, issuing VECTRESET", reset_addr);
+ LOG_INFO("psoc6.cm4: bkpt @0x%08" PRIX32 ", issuing VECTRESET", reset_addr);
mem_ap_write_atomic_u32(cm->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_VECTRESET);
}
/* Check for valid size */
if (wordcount > bufferwsize) {
- LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
- PRId32, wordcount, buffersize);
+ LOG_ERROR("Number of data words %" PRIu32 " exceeds available buffersize %"
+ PRIu32, wordcount, buffersize);
return ERROR_FLASH_OPERATION_FAILED;
}
/* handle unaligned tail bytes */
if (count > 0) {
- LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
+ LOG_INFO("Fixup %" PRIu32 " unaligned tail bytes", count);
/* read a complete word from flash */
retval = cfi_target_read_memory(bank, write_p, 1, current_word);
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
- LOG_DEBUG("reading buffer of %" PRIi32 " byte at 0x%8.8" PRIx32,
+ LOG_DEBUG("reading buffer of %" PRIu32 " byte at 0x%8.8" PRIx32,
count, offset);
if (bank->target->state != TARGET_HALTED) {
}
if (offset & 0xff) {
- LOG_ERROR("sh_qspi_write_page: unaligned write address: %08x",
+ LOG_ERROR("sh_qspi_write_page: unaligned write address: %08" PRIx32,
offset);
return ERROR_FAIL;
}
const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
if (gap_size_kb != 0) {
- LOG_INFO("gap detected from 0x%08" PRIx32 " to 0x%08" PRIx32,
+ LOG_INFO("gap detected from 0x%08x to 0x%08x",
STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
* page_size_kb * 1024,
STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
/* Make sure we're performing a half-page aligned write. */
if (count % hp_nb) {
- LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIi32 "B)", hp_nb, count);
+ LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIu32 "B)", hp_nb, count);
return ERROR_FAIL;
}
protect_state = "protection state unknown";
command_print(CMD,
- "\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
+ "\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIu32 "kB) %s",
j,
block_array[j].offset,
block_array[j].size,
blank = false;
command_print(CMD,
- "\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIi32 "kB) %s",
+ "\t#%3i: 0x%8.8" PRIx32 " (0x%" PRIx32 " %" PRIu32 "kB) %s",
j,
p->sectors[j].offset,
p->sectors[j].size,
retval = flash_erase_address_range(target, do_pad, address, length);
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
- command_print(CMD, "erased address " TARGET_ADDR_FMT " (length %"
- PRIi32 ")"
+ command_print(CMD, "erased address " TARGET_ADDR_FMT " (length %" PRIu32 ")"
" in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
}
if (!(last <= (p->num_sectors - 1))) {
command_print(CMD, "ERROR: "
- "last sector must be <= %" PRIu32,
+ "last sector must be <= %u",
p->num_sectors - 1);
return ERROR_FAIL;
}
if (!(last <= (uint32_t)(num_blocks - 1))) {
command_print(CMD, "ERROR: "
- "last %s must be <= %" PRIu32,
+ "last %s must be <= %d",
(p->num_prot_blocks) ? "block" : "sector",
num_blocks - 1);
return ERROR_FAIL;
LOG_WARNING("Start address " TARGET_ADDR_FMT
" breaks the required alignment of flash bank %s",
address, bank->name);
- LOG_WARNING("Padding %" PRId32 " bytes from " TARGET_ADDR_FMT,
+ LOG_WARNING("Padding %" PRIu32 " bytes from " TARGET_ADDR_FMT,
padding_at_start, aligned_start);
}
if (padding_at_end) {
memset(ptr, bank->default_padded_value, padding_at_end);
- LOG_INFO("Padding at " TARGET_ADDR_FMT " with %" PRId32
+ LOG_INFO("Padding at " TARGET_ADDR_FMT " with %" PRIu32
" bytes (bank write end alignment)",
end_addr + 1, padding_at_end);
}
LOG_WARNING("Start offset 0x%08" PRIx32
" breaks the required alignment of flash bank %s",
offset, bank->name);
- LOG_WARNING("Padding %" PRId32 " bytes from " TARGET_ADDR_FMT,
+ LOG_WARNING("Padding %" PRIu32 " bytes from " TARGET_ADDR_FMT,
padding_at_start, aligned_start);
}
if (padding_at_end) {
memset(ptr, bank->default_padded_value, padding_at_end);
- LOG_INFO("Padding at " TARGET_ADDR_FMT " with %" PRId32
+ LOG_INFO("Padding at " TARGET_ADDR_FMT " with %" PRIu32
" bytes (bank write end alignment)",
end_addr + 1, padding_at_end);
}
for (t = 0; t < length; t++) {
if (buffer_flash[t] == buffer_file[t])
continue;
- command_print(CMD, "diff %d address 0x%08x. Was 0x%02x instead of 0x%02x",
+ command_print(CMD, "diff %d address 0x%08" PRIx32 ". Was 0x%02x instead of 0x%02x",
diffs, t + offset, buffer_flash[t], buffer_file[t]);
if (diffs++ >= 127) {
command_print(CMD, "More than 128 errors, the rest are not printed.");
tms470_read_part_info(bank);
- LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
+ LOG_INFO("Writing %" PRIu32 " bytes starting at " TARGET_ADDR_FMT,
count, bank->base + offset);
/* set GLBCTRL.4 */
}
if ((offset % W600_FLASH_PAGESIZE) != 0) {
- LOG_WARNING("offset 0x%" PRIx32 " breaks required %" PRIu32 "-byte alignment",
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required %d-byte alignment",
offset, W600_FLASH_PAGESIZE);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
if ((count % W600_FLASH_PAGESIZE) != 0) {
- LOG_WARNING("count 0x%" PRIx32 " breaks required %" PRIu32 "-byte alignment",
+ LOG_WARNING("count 0x%" PRIx32 " breaks required %d-byte alignment",
offset, W600_FLASH_PAGESIZE);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
flash_size = 1 << flash_size;
}
- LOG_INFO("flash size = %dkbytes", flash_size / 1024);
+ LOG_INFO("flash size = %" PRIu32 "kbytes", flash_size / 1024);
/* calculate numbers of pages */
size_t num_pages = flash_size / W600_FLASH_SECSIZE;
bank->num_sectors = 4;
break;
default:
- LOG_ERROR("Unknown flash device ID 0x%X", id);
+ LOG_ERROR("Unknown flash device ID 0x%" PRIX32, id);
return ERROR_FAIL;
}
bank->driver_priv = priv;
LOG_INFO("product name: %s", product_name(bank));
- LOG_INFO("device id = 0x%X ", bank->target->tap->idcode);
+ LOG_INFO("device id = 0x%" PRIX32, bank->target->tap->idcode);
LOG_INFO("flash size = %d configuration bits",
bank->num_sectors * XCF_DATA_SECTOR_SIZE * 8);
LOG_INFO("number of sectors = %u", bank->num_sectors);
#include "../../../contrib/loaders/flash/xmc1xxx/write.inc"
};
- LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRId32 " bytes)",
+ LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
offset, byte_count);
if (offset & (NVM_BLOCK_SIZE - 1)) {
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
if (byte_count & (NVM_BLOCK_SIZE - 1)) {
- LOG_WARNING("length %" PRId32 " is not block aligned, rounding up",
+ LOG_WARNING("length %" PRIu32 " is not block aligned, rounding up",
byte_count);
}
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
uint32_t addr = bank->base + offset;
- LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
+ LOG_DEBUG("copying %" PRIu32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
data_workarea->address);
}
}
- LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRId32 "x)",
+ LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRIu32 "x)",
addr, addr + blocks * NVM_BLOCK_SIZE - 1, blocks);
retval = xmc1xxx_nvm_check_idle(target);
}
LOG_DEBUG("ID[7] = %08" PRIX32, chipid[7]);
- snprintf(buf, buf_size, "XMC%" PRIx32 "00 %X flash %uKB ROM %uKB SRAM %uKB",
+ snprintf(buf, buf_size, "XMC%" PRIx32 "00 %" PRIX32 " flash %" PRIu32 "KB ROM %" PRIu32 "KB SRAM %" PRIu32 "KB",
(chipid[0] >> 12) & 0xff,
0xAA + (chipid[7] >> 28) - 1,
(((chipid[6] >> 12) & 0x3f) - 1) * 4,
Code Review / openocd.git / commitdiff