tcl/stm32mp15x: freeze watchdog, recover SWD after power cycle

Freeze the IWDG watchdog when cores are halted to prevent a reset
while debugging.

The PMIC present on some board senses the nsrst and forces a power
cycle to the target. The power cycle causes the SWJ-DP to restart
in JTAG mode. If the debugger is using SWD, the mismatch triggers
an error after the reset command.
Ignore the error detected by 'dap init' and proceed executing the
handler. The error in 'dap init' will force a reconnect during the
following 'dap apid', restoring the SWD functionality.

Change-Id: I04fcda6a5b8a1b080ab4e8890ecd0754d5ed12d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6599
Tested-by: jenkins

diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index e50ef9c20ec70373b165f48e529b41022c9822d0..639fbabe06e9dc23a0b56cf70a174024e513724c 100644 (file)
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -97,6 +97,9 @@ axi_secure
 proc dbgmcu_enable_debug {} {
        # set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
        catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
 proc dbgmcu_enable_debug {} {
        # set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
        catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}

+       # freeze watchdog 1 and 2 on cores halted
+       catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+       catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}

 }
 
 proc toggle_cpu0_dbg_claim0 {} {
 }
 
 proc toggle_cpu0_dbg_claim0 {} {


@@ -116,7 +119,7 @@ proc rcc_enable_traceclk {} {
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged

-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}

 $_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
 $_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}