pld/virtex2: small doc extension

Change-Id: I174cd702388be04268b38178fbfacb90db452f72
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7303
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0fd2322f2e2dcb49c37dd87f53dfff1d76ef9494..e9f93614c93ab49f24d2f2a64b3d11d337eb20da 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8478,12 +8478,20 @@ that particular type of PLD.
 
 @deffn {FPGA Driver} {virtex2} [no_jstart]
 Virtex-II is a family of FPGAs sold by Xilinx.
+This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices.
 It supports the IEEE 1532 standard for In-System Configuration (ISC).
 
 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
 loading the bitstream. While required for Series2, Series3, and Series6, it
 breaks bitstream loading on Series7.
 
+@example
+openocd -f board/digilent_zedboard.cfg -c "init" \
+       -c "pld load 0 zedboard_bitstream.bit"
+@end example
+
+
+
 @deffn {Command} {virtex2 read_stat} num
 Reads and displays the Virtex-II status register (STAT)
 for FPGA @var{num}.