oharboe [Wed, 26 Aug 2009 10:03:54 +0000 (10:03 +0000)]
Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then simulation will fail. This is expected.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2629
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Wed, 26 Aug 2009 08:32:03 +0000 (08:32 +0000)]
reduce arm11 output noise
git-svn-id: svn://svn.berlios.de/openocd/trunk@2628
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Wed, 26 Aug 2009 07:11:16 +0000 (07:11 +0000)]
Michael Schwingen <rincewind@discworld.dascon.de> news about xscale
git-svn-id: svn://svn.berlios.de/openocd/trunk@2627
b42882b7-edfa-0310-969c-
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oharboe [Wed, 26 Aug 2009 06:26:29 +0000 (06:26 +0000)]
David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris flash driver:
- Bugfixes:
* internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
+ except new Tempest parts where it's 16 MHz (and calibrated!)
+ or some old Sandstorm ones, where 15 MHz was valid
* crystal config:
+ read and use the crystal config, don't assume 6 MHz
+ know when that field is 4 bits vs 5
* an RCC2 register may be overriding the original RCC
+ more clock source options
+ bigger dividers
+ fractional dividers on Tempest (NYET handled)
* there's a 30 KHz osc on newer chips (for deep sleep)
* there's a 32768 Hz osc on newer chips (for hibernation)
- Cosmetic
* say "rev A0" not "vA.0", to match vendor docs
* don't always report master clock as an "estimate":
+ give the error bound if it's approximate, like "±30%"
+ else don't say anything
* fix whitespace and caps in some messages
* these are not AT91SAM chips!!
Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.
That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor. What's less clear is which chips are "old" like that.
Lightly tested, on a DustDevil part.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2626
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 20:03:35 +0000 (20:03 +0000)]
David Brownell <david-b@pacbell.net> Various updates to 0.3.0 NEWS
git-svn-id: svn://svn.berlios.de/openocd/trunk@2625
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 20:02:19 +0000 (20:02 +0000)]
David Brownell <david-b@pacbell.net> Tweak disassembly commands:
For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 19:59:55 +0000 (19:59 +0000)]
David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:
Unify the handling of the req_srst parameter, and rip out a
large NOP branch and its associated FIXME. (There didn't seem
to be anything that needs fixing; but that was unclear since
the constraints were scattered all over the place not unified.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2623
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 19:58:06 +0000 (19:58 +0000)]
David Brownell <david-b@pacbell.net> More jtag_add_reset() cleanup:
Unify the handling of the req_tlr_or_trst parameter. Basically,
JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe
option in this system configuration.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2622
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 19:55:32 +0000 (19:55 +0000)]
David Brownell <david-b@pacbell.net> Some jtag_add_reset() cleanup:
- Track whether TRST and/or SRST actually change:
* If they're not changing, don't ask the JTAG adapter to do anything!
(JTAG TCK/TMS ops might still be used to enter TAP_RESET though.)
* Don't change their recorded values until after the adapter says it
did so ... so fault paths can't leave corrupt state.
* Detect and report jtag_execute_queue() failure mode
* Only emit messages saying what really changed; this includes adding
an omitted "deasserted TRST" message.
* Only apply delays after deasserting SRST/TRST if we *DID* deassert!
- Messages say "TLR" not "RESET", to be less confusing; there are many
kinds of reset. (Though "TLR" isn't quite ideal either, since it's
the name of the TAP state being entered by TMS+TCK or TRST; it's at
least non-ambiguous in context.)
So the main effect is to do only the work this routine was told to do;
and to have debug messaging make more sense.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2621
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 19:52:02 +0000 (19:52 +0000)]
David Brownell <david-b@pacbell.net> Accomodate targets which don't support various target-specific
reset operations. Maybe they can't; or it's a "not yet" thing.
Note that the assert/deassert operations can't yet trigger for
OMAP3 because resets currently include JTAG reset in all cases,
resetting the ICEpick and thus disabling the TAP for Cortex-A8.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2620
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 13:00:45 +0000 (13:00 +0000)]
Michael Schwingen <rincewind@discworld.dascon.de> fix previous doc patch
git-svn-id: svn://svn.berlios.de/openocd/trunk@2619
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 25 Aug 2009 12:19:44 +0000 (12:19 +0000)]
- fix build warnings
- add svn props to recently added files armv7a.[ch]
git-svn-id: svn://svn.berlios.de/openocd/trunk@2618
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 08:21:11 +0000 (08:21 +0000)]
Michael Schwingen <rincewind@discworld.dascon.de> a small CFI cleanup
git-svn-id: svn://svn.berlios.de/openocd/trunk@2617
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 07:17:19 +0000 (07:17 +0000)]
strange.... the code build and links w/Linux GCC target but fails w/arm-elf. The code was clearly broken as it was missing two extern's in the .h file...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2616
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 07:14:05 +0000 (07:14 +0000)]
Ferdinand Postema <ferdinand@postema.eu> fix warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2615
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 07:12:57 +0000 (07:12 +0000)]
Ferdinand Postema <ferdinand@postema.eu> increase reset delay to fix regression from 2600 to 2604
git-svn-id: svn://svn.berlios.de/openocd/trunk@2614
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 07:09:48 +0000 (07:09 +0000)]
Michael Schwingen <rincewind@discworld.dascon.de> The attached patch adds a "xscale vector_table" command that allows to set
the values that are written in the mini-IC (plus documentation updates that
describe why this is needed).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2613
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
oharboe [Tue, 25 Aug 2009 07:04:25 +0000 (07:04 +0000)]
Audrius Urmanavičius <didele.deze@gmail.com> Latest source (R2606) does not compile under Windows+Cygwin - fails with error about possibly uninitialized use of variable 'ch'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2612
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 07:02:50 +0000 (07:02 +0000)]
Brian Findlay <findlaybrian@gmail.com> finalize mini2440.cfg
git-svn-id: svn://svn.berlios.de/openocd/trunk@2611
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 06:59:42 +0000 (06:59 +0000)]
use cortex_a8 instead of cortex_m3
git-svn-id: svn://svn.berlios.de/openocd/trunk@2610
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 06:58:34 +0000 (06:58 +0000)]
David Brownell The rest of the Cortex-A8 support from Magnus: replace the previous
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from Øyvind, and cleanup from Dave.)
This code has mainly been developed and tested against R1606, it has
been built and tested against R2294 where it runs but step and resume
commands are broken due to regression (which should be fixed now).
This code is really written for OMAP3530. It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection. The OMAP3530 DAP exposes two memory access ports:
- Port #0 is connected to L3 interconnect (the main bus) with
passthrough to the L4 EMU bus ... so it will be used for most
memory accesses.
- Port #1 is connected to a dedicated debug bus (L4 EMU), with
access to L4 Wakeup, and holds the ROM table ... so it must
be used for most debug and control operations.
The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code. Having access to another Cortex-A8
implementation would help get that right.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2609
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 06:57:26 +0000 (06:57 +0000)]
David Brownell Subset of Cortex-A8 support from Magnus: create an armv7a file
and seed it with DAP access support using the current ADIv5 code.
(With tweaks and cleanup from Øyvind and Dave.)
The ARMv7-AR architecture manual is not publicly available (even
in subset form like the ARMv7-M spec), so it's hard to distinguish
between the Cortex-A8 implementation and the ARMv7-A architecture.
The register set presumably is architectural, and so it's stored
here; it's like earlier ARMs, with small additions. Ditto the
instruction set, though Thumb2 support is used (extending Thumb
support from ARMv6 with more 32-bit instructions) and there's this
ThumbEE thing too. There is a new "debug monitor" mode, not yet
fully addressed here, to support debugging in environments (like
motor control) where halting debug mode is inadvisable.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2608
b42882b7-edfa-0310-969c-
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oharboe [Tue, 25 Aug 2009 06:45:40 +0000 (06:45 +0000)]
add missing isblank() for eCos
git-svn-id: svn://svn.berlios.de/openocd/trunk@2607
b42882b7-edfa-0310-969c-
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oharboe [Mon, 24 Aug 2009 07:53:46 +0000 (07:53 +0000)]
Steve Grubb <sgrubb@redhat.com> fix various and sundry leaks
git-svn-id: svn://svn.berlios.de/openocd/trunk@2606
b42882b7-edfa-0310-969c-
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oharboe [Mon, 24 Aug 2009 07:26:05 +0000 (07:26 +0000)]
Jonas Horberg <jhorberg@sauer-danfoss.com>
The trunk is currently broken for interfaces without
the speed_div function (interface specific clock speed
value to kHz conversion). Example: parport.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2605
b42882b7-edfa-0310-969c-
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oharboe [Fri, 21 Aug 2009 11:23:24 +0000 (11:23 +0000)]
Pieter Conradie <Pieter.Conradie@psitek.com> shuffle things around to the right spots. Should have been done in previous commit.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2604
b42882b7-edfa-0310-969c-
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oharboe [Fri, 21 Aug 2009 09:01:00 +0000 (09:01 +0000)]
native line endings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2603
b42882b7-edfa-0310-969c-
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oharboe [Fri, 21 Aug 2009 08:58:49 +0000 (08:58 +0000)]
Pieter Conradie <Pieter.Conradie@psitek.com> Scripts for Atmel AT91SAM7S256 and AT91SAM9260
git-svn-id: svn://svn.berlios.de/openocd/trunk@2602
b42882b7-edfa-0310-969c-
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oharboe [Fri, 21 Aug 2009 06:22:01 +0000 (06:22 +0000)]
Florian Boor <florian.boor@kernelconcepts.de> fixes a segfault executing commands from the web interface using the
"Run Command" tab.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2601
b42882b7-edfa-0310-969c-
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oharboe [Thu, 20 Aug 2009 08:55:34 +0000 (08:55 +0000)]
Piotr Ziecik <kosmo@semihalf.com> This patch adds handling blank characters between hex digits in
SVF file, making OpenOCD compatible with files generated by
Altera Quatrus II 9.0.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2600
b42882b7-edfa-0310-969c-
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ntfreak [Thu, 20 Aug 2009 07:54:49 +0000 (07:54 +0000)]
- remove enable-ft2232-highspeed configure option, high speed ftdi support is now detected during the configure stage
- warning now issued if high speed ftdi device found and openocd was built using an old driver
git-svn-id: svn://svn.berlios.de/openocd/trunk@2599
b42882b7-edfa-0310-969c-
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oharboe [Thu, 20 Aug 2009 07:15:46 +0000 (07:15 +0000)]
David Brownell <david-b@pacbell.net>More Thumb2 disassembly:
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch
GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler. LDREX and STREX are not
issued by GCC without inline assembly.
This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled. Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2598
b42882b7-edfa-0310-969c-
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ntfreak [Wed, 19 Aug 2009 08:39:06 +0000 (08:39 +0000)]
Jonas Horberg [jhorberg@sauer-danfoss.com]:
Fix small typo in ftd2xx type detection
git-svn-id: svn://svn.berlios.de/openocd/trunk@2597
b42882b7-edfa-0310-969c-
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oharboe [Wed, 19 Aug 2009 06:31:44 +0000 (06:31 +0000)]
David Brownell <david-b@pacbell.net>Fix some command helptext:
- spell "address" right
- list bp/wp params as optional
And make those source lines wrap at sane margins.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2596
b42882b7-edfa-0310-969c-
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oharboe [Wed, 19 Aug 2009 06:30:08 +0000 (06:30 +0000)]
David Brownell <david-b@pacbell.net> Clean up some Cortex-M3 reset handling.
- AIRCR_SYSRESETREQ is generic; use it on any system where
SRST won't fly, not just on Stellaris-based ones.
- Reformat and improve comments about the Stellaris quirk; and
xref the only public docs (an email) about the issue.
It seems that *most* Stellaris chips have this problem. Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2595
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 18 Aug 2009 19:55:01 +0000 (19:55 +0000)]
David Brownell [david-b@pacbell.net]:
Simplify dumping of register lists by only printing cached values
if they are marked as valid. Most of the time, they are invalid;
so printing *any* value is just misleading.
Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2594
b42882b7-edfa-0310-969c-
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oharboe [Tue, 18 Aug 2009 17:57:19 +0000 (17:57 +0000)]
Brian Findlay <findlaybrian@gmail.com> Board support for mini2440 (friendlyARM) samsung s3c2440 based board
git-svn-id: svn://svn.berlios.de/openocd/trunk@2593
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 18 Aug 2009 16:46:48 +0000 (16:46 +0000)]
- add cfg file for Amontec JTAGKey2 jtag interface
git-svn-id: svn://svn.berlios.de/openocd/trunk@2592
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 18 Aug 2009 14:41:58 +0000 (14:41 +0000)]
Jonas Horberg [jhorberg@sauer-danfoss.com]
https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html
1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H
since version 0.16
2. A speed value of 0 is used as a RTCK request indicator. This clashes with the
valid clock division value 0 that provide the highest fixed clock frequency.
3. The ft2232_speed_div function return the maximum selectable frequency (30MHz)
when RTCK is activated. It should return 0.
4. The ft2232_khz function return ERROR_OK when RTCK is requested even for
devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers
can detect this and try to fallback to a fixed frequency.
5. FT2232H/FT4232H have a backward compatibility function that divide the clock
by 5 to get the same frequency range as FT2232D. There is no code that disable
this functionality. I can not find anything about if this is enabled or disabled by default.
I think it is safest to actively disable it.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2591
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 18 Aug 2009 12:14:01 +0000 (12:14 +0000)]
Jonas Horberg [jhorberg@sauer-danfoss.com]
Change jtag_rclk behaviour so it can be called before the interface init function
git-svn-id: svn://svn.berlios.de/openocd/trunk@2590
b42882b7-edfa-0310-969c-
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oharboe [Tue, 18 Aug 2009 10:27:24 +0000 (10:27 +0000)]
David Brownell <david-b@pacbell.net> Cleanup the Stellaris target configs:
- remove endianness options; these chips hard-wire "little"
- $_TARGETNAME updates:
* don't pass $_TARGETNAME where a TAP label is required
* flash config uses $_TARGETNAME (it might not be target #0)
* simplify one $_TARGETNAME construction
- update work area setup:
* remove VM spec; these chips have no VM!
* fix some wrong sizes (0x4000 == 16K, not 4K)
* simplify: take defaults
- comment fixups
git-svn-id: svn://svn.berlios.de/openocd/trunk@2589
b42882b7-edfa-0310-969c-
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oharboe [Tue, 18 Aug 2009 10:25:28 +0000 (10:25 +0000)]
David Brownell <david-b@pacbell.net> Add "cortex_m3 vector_catch" command and docs. One minor
issue with this is that the core debug support uses this
mechanism, then trashes its state over reset. Users can
Work around that (for now) by re-assigning the desired
config after reset.
Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2588
b42882b7-edfa-0310-969c-
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oharboe [Tue, 18 Aug 2009 10:22:44 +0000 (10:22 +0000)]
David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register handling ... don't use parallel
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.
Minor updates for ARM9 vector_catch support: it's an 8-bit value. This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2587
b42882b7-edfa-0310-969c-
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oharboe [Tue, 18 Aug 2009 10:20:25 +0000 (10:20 +0000)]
David Brownell <david-b@pacbell.net> Several of the ARMv7M registers are 8 bits or less; don't
display them as 32 bits unless that's their true size.
(Removes some confusion.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2586
b42882b7-edfa-0310-969c-
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oharboe [Tue, 18 Aug 2009 10:18:18 +0000 (10:18 +0000)]
Piotr Ziecik <kosmo@semihalf.com> Due to errors in chipselect management in davinci_nand driver
OpenOCD was able to access only to chips attached to first EMIF
chipselect. This patch fixes chipselect management code and allows
OpenOCD to access to NAND devices attached to any EMIF CS line.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2585
b42882b7-edfa-0310-969c-
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oharboe [Sun, 16 Aug 2009 12:08:35 +0000 (12:08 +0000)]
Xiaofan Chen <xiaofanc@gmail.com> Split LM3S811 config file into target file and board file
git-svn-id: svn://svn.berlios.de/openocd/trunk@2584
b42882b7-edfa-0310-969c-
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oharboe [Sun, 16 Aug 2009 11:58:40 +0000 (11:58 +0000)]
michal smulski <michal.smulski@ooma.com> arm11 target config files
git-svn-id: svn://svn.berlios.de/openocd/trunk@2583
b42882b7-edfa-0310-969c-
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oharboe [Sun, 16 Aug 2009 11:54:56 +0000 (11:54 +0000)]
Xiaofan Chen <xiaofanc@gmail.com> Add config file for TI-Luminary LM3S1968 chip and EK-LM3S1968 board
git-svn-id: svn://svn.berlios.de/openocd/trunk@2582
b42882b7-edfa-0310-969c-
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oharboe [Sun, 16 Aug 2009 11:52:50 +0000 (11:52 +0000)]
Ferdinand Postema <ferdinand@postema.eu> cygwin 32 bit warning
git-svn-id: svn://svn.berlios.de/openocd/trunk@2581
b42882b7-edfa-0310-969c-
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oharboe [Sun, 16 Aug 2009 11:49:21 +0000 (11:49 +0000)]
added note w/reference to discussion on whether or not arm11 code is broken or not.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2580
b42882b7-edfa-0310-969c-
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ntfreak [Thu, 13 Aug 2009 13:54:53 +0000 (13:54 +0000)]
Audrius Urmanavičius [didele.deze@gmail.com]:
Add flash programming support for NXP LPC1700 cortex_m3 based family
git-svn-id: svn://svn.berlios.de/openocd/trunk@2579
b42882b7-edfa-0310-969c-
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ntfreak [Fri, 7 Aug 2009 09:37:59 +0000 (09:37 +0000)]
David Brownell <david-b@pacbell.net>:
Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2578
b42882b7-edfa-0310-969c-
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ntfreak [Fri, 7 Aug 2009 09:29:41 +0000 (09:29 +0000)]
David Brownell <david-b@pacbell.net>:
Better explanation for the TAP "-ircapture" parameter.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2577
b42882b7-edfa-0310-969c-
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ntfreak [Fri, 7 Aug 2009 09:19:06 +0000 (09:19 +0000)]
Ferdinand Postema [ferdinand@postema.eu]
- fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9
git-svn-id: svn://svn.berlios.de/openocd/trunk@2576
b42882b7-edfa-0310-969c-
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ntfreak [Fri, 7 Aug 2009 09:09:06 +0000 (09:09 +0000)]
- fix segfault introduced during cortex reg cleanup
git-svn-id: svn://svn.berlios.de/openocd/trunk@2575
b42882b7-edfa-0310-969c-
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ntfreak [Thu, 6 Aug 2009 23:34:34 +0000 (23:34 +0000)]
Gary Carlson [gcarlson@carlson-minot.com]:
- revert patch from rev1507 as it was causing reset issues with arm9 cores
git-svn-id: svn://svn.berlios.de/openocd/trunk@2574
b42882b7-edfa-0310-969c-
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ntfreak [Thu, 6 Aug 2009 21:44:18 +0000 (21:44 +0000)]
- Bring all the ftdi names inline in the cfg scripts. scripts will now work for either ftd2xx or libftdi drivers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2573
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zwelch [Thu, 6 Aug 2009 19:52:56 +0000 (19:52 +0000)]
michal smulski <michal.smulski@ooma.com>:
Fix ARM11 half-word bulk memory read and write.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2572
b42882b7-edfa-0310-969c-
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ntfreak [Fri, 31 Jul 2009 08:52:03 +0000 (08:52 +0000)]
- add configure error if building parport interface under cygwin and sys/io.h missing
git-svn-id: svn://svn.berlios.de/openocd/trunk@2571
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oharboe [Mon, 27 Jul 2009 18:56:43 +0000 (18:56 +0000)]
Fix NPE in GDB_EVENT_END as logforwarding was not disabled early enough
git-svn-id: svn://svn.berlios.de/openocd/trunk@2570
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oharboe [Mon, 27 Jul 2009 14:46:49 +0000 (14:46 +0000)]
add "dummy" interface trick to the BUGS reporting suggestions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2569
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oharboe [Sun, 26 Jul 2009 20:00:39 +0000 (20:00 +0000)]
David Brownell <david-b@pacbell.net> More testcase work:
A5.3.11 Data processing (shifted register)
The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes. There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2568
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oharboe [Sun, 26 Jul 2009 19:59:33 +0000 (19:59 +0000)]
More instruction decoding fixes:
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2567
b42882b7-edfa-0310-969c-
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oharboe [Sun, 26 Jul 2009 19:58:25 +0000 (19:58 +0000)]
David Brownell <david-b@pacbell.net> More fixes from test cases:
A5.3.8 Load halfword, unallocated memory hints
It's mostly the usual sort of bitmasking goofage and getting the
width specs right. In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2566
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oharboe [Sun, 26 Jul 2009 19:56:58 +0000 (19:56 +0000)]
David Brownell <david-b@pacbell.net> More instruction decoding fixes:
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2565
b42882b7-edfa-0310-969c-
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oharboe [Fri, 24 Jul 2009 16:49:44 +0000 (16:49 +0000)]
David Brownell <david-b@pacbell.net> More instruction decoding fixes based on test cases, covering
ARMv7-M arch manual:
A5.3.1 Data processing (modified immediate)
A5.3.3 Data processing (plain binary immediate)
A5.3.4 Branches and miscellaneous control
and other (immediate) encodings referenced there. Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2564
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oharboe [Fri, 24 Jul 2009 16:48:12 +0000 (16:48 +0000)]
David Brownell <david-b@pacbell.net> Bugfix some instruction decoding ... I've crafted asm files
with testcases covering several new encodings in these sections
of the ARMv7-M arch manual:
A5.3.12 Data processing (register)
A5.3.13 Miscellaneous operations
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, and divide
The issues were mostly in '12 and '13; some new related 16-bit
opcodes had issues too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2563
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oharboe [Fri, 24 Jul 2009 05:42:45 +0000 (05:42 +0000)]
Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few checks for (rt == 0xf) even though that case
is handled with an early return at the top of the function.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2562
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oharboe [Thu, 23 Jul 2009 15:35:16 +0000 (15:35 +0000)]
David Brownell <david-b@pacbell.net> thumb2 disassembly for Load halfword
git-svn-id: svn://svn.berlios.de/openocd/trunk@2561
b42882b7-edfa-0310-969c-
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oharboe [Thu, 23 Jul 2009 15:34:03 +0000 (15:34 +0000)]
David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, memory hints
git-svn-id: svn://svn.berlios.de/openocd/trunk@2560
b42882b7-edfa-0310-969c-
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oharboe [Thu, 23 Jul 2009 07:04:21 +0000 (07:04 +0000)]
Ferdinand Postema <ferdinand@postema.eu> fix cygwin warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2559
b42882b7-edfa-0310-969c-
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oharboe [Thu, 23 Jul 2009 07:02:43 +0000 (07:02 +0000)]
David Brownell <david-b@pacbell.net> fix warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2558
b42882b7-edfa-0310-969c-
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oharboe [Wed, 22 Jul 2009 19:35:23 +0000 (19:35 +0000)]
Jonathan Cameron <jic23@cam.ac.uk> fix regression from 1836 when the reset_config command was removed from pxa270.cfg
git-svn-id: svn://svn.berlios.de/openocd/trunk@2557
b42882b7-edfa-0310-969c-
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oharboe [Wed, 22 Jul 2009 14:25:56 +0000 (14:25 +0000)]
Stefano Voulaz <s.voulaz@projecktstudio.com> first cut samsung_s3c2450
git-svn-id: svn://svn.berlios.de/openocd/trunk@2556
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ntfreak [Tue, 21 Jul 2009 20:19:02 +0000 (20:19 +0000)]
David Brownell <david-b@pacbell.net>:
Dump SP on poll, and show whether it's MSP or PSP.
Thread mode can use either stack pointer, so this is
part of the state that's not yet displayed.
Shrink some lines.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2555
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 21 Jul 2009 20:15:11 +0000 (20:15 +0000)]
David Brownell <david-b@pacbell.net>:
Clean up treatment of registers in ARMv7-M and Cortex-M3.
- At the arch level:
* Just list registers and names; don't impose core-specific
policy about how they are accessed.
* Each register has a symbol.
* Remove the register mode field (irrelevant to debugger)
- At the core/implementation level:
* Just map the registers to their relevant access methods;
don't require the arch level to say how that should work
(cores other than Cortex-M3 could do it differently).
* Don't use undefined bits from register 20.
* Use register IDs that are part of the ARMv7-M interface.
In short, there's now a real distinction between the arch
and core layers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2554
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 21 Jul 2009 20:05:05 +0000 (20:05 +0000)]
David Brownell <david-b@pacbell.net>:
Minor updates to the Thumb2 disassembly:
- Bugfixes:
* Distinguish branch from misc via "!=" not "=="
* MRS register shift is 8 bits (vs MSR being 16)
- Format tweaks:
* CPS needed tab (not space)
* add commma before some shifts
* add space after comma in LDM/STM
* use ".W" width spec on various instructions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2553
b42882b7-edfa-0310-969c-
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ntfreak [Tue, 21 Jul 2009 20:03:17 +0000 (20:03 +0000)]
David Brownell <david-b@pacbell.net>:
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2552
b42882b7-edfa-0310-969c-
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ntfreak [Mon, 20 Jul 2009 07:03:11 +0000 (07:03 +0000)]
- fix issue with reading device id, bug appeared when flash_address code was added
- fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus
git-svn-id: svn://svn.berlios.de/openocd/trunk@2551
b42882b7-edfa-0310-969c-
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oharboe [Sun, 19 Jul 2009 19:31:54 +0000 (19:31 +0000)]
aduc flash problems have been resolved
git-svn-id: svn://svn.berlios.de/openocd/trunk@2550
b42882b7-edfa-0310-969c-
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oharboe [Fri, 17 Jul 2009 19:54:25 +0000 (19:54 +0000)]
Andreas Fritiofson <andreas.fritiofson@gmail.com> UTF8 fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@2549
b42882b7-edfa-0310-969c-
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oharboe [Thu, 16 Jul 2009 10:44:42 +0000 (10:44 +0000)]
added item to come up with slick new 32 bit jtag_add_xxx() API
git-svn-id: svn://svn.berlios.de/openocd/trunk@2548
b42882b7-edfa-0310-969c-
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oharboe [Thu, 16 Jul 2009 10:43:15 +0000 (10:43 +0000)]
microscopic whitespace cleanup
git-svn-id: svn://svn.berlios.de/openocd/trunk@2547
b42882b7-edfa-0310-969c-
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oharboe [Thu, 16 Jul 2009 10:30:50 +0000 (10:30 +0000)]
microscopic white space fixes
git-svn-id: svn://svn.berlios.de/openocd/trunk@2546
b42882b7-edfa-0310-969c-
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ntfreak [Thu, 16 Jul 2009 10:03:33 +0000 (10:03 +0000)]
- disable using parport ppdev under win32 hosts
git-svn-id: svn://svn.berlios.de/openocd/trunk@2545
b42882b7-edfa-0310-969c-
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zwelch [Thu, 16 Jul 2009 00:08:36 +0000 (00:08 +0000)]
Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c. There should be no
change in functionality here. (From Magnus.)
Minor style cleanup: whitespace, line length, etc. Update spec
references to use docs which are currently available. (From Dave.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2544
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zwelch [Thu, 16 Jul 2009 00:08:21 +0000 (00:08 +0000)]
Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543
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zwelch [Wed, 15 Jul 2009 23:49:12 +0000 (23:49 +0000)]
David Brownell <david-b@pacbell.net>:
More 32-bit Thumb2 instruction decoding:
A5.3.7 Load word
git-svn-id: svn://svn.berlios.de/openocd/trunk@2542
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zwelch [Wed, 15 Jul 2009 23:49:05 +0000 (23:49 +0000)]
David Brownell <david-b@pacbell.net>:
More 32-bit Thumb2 instruction decoding:
A5.3.12 Data processing (register)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2541
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:49:00 +0000 (23:49 +0000)]
David Brownell <david-b@pacbell.net>:
More 32-bit instruction decoding:
A5.3.11 Data processing (shifted register)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2540
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:54 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
More instructions decoded:
A5.3.5 Load/store multiple
The preferred PUSH/POP syntax is shown when appropriate.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2539
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:43 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
More instructions decoded:
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, divide
The EABI requires *adjacent* register pairs, but the long multiply
ops can use any pair of registers; interesting.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2538
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:37 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
More Thumb2 32-bit opcode support:
A5.3.10 Store single data item
Byte, word, halfword. Offset, pre-index, post-index. And
a "make like you're unprivileged" option when using small
immediate offsets.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2537
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:32 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
Print old-style Thumb NOP instructions as such. (GCC uses "mov r8, r8"
instead of the architected NOP which is new in Thumb2.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2536
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:27 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
Make disassembly of the Thumb load-literal instruction show the
address of the literal being loaded (so users can avoid doing
that math themselves). Add and use an Align(PC,4) utility.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2535
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:21 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle more 32-bit instructions:
A5.3.3 Data processing (plain binary immediate)
These use mostly twelve bit literals, but there are also bitfield
and saturated add primitives.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2534
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:16 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle more 32-bit instructions:
A5.3.1 Data processing (modified immediate)
My small sample shows GCC likes to use many of these instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2533
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:48:11 +0000 (23:48 +0000)]
David Brownell <david-b@pacbell.net>:
Make the Thumb2 disassembler handle a bunch of 32-bit instructions:
A5.3.4 Branches and miscellaneous control
Note that this shifts some responsabililty out of helper functions,
making the code and layout simpler for 32-bit decoders: they only
need to know how to format the instruction and its parameters.
Also, technical note: with this patch, Thumb1 decoders could now
call the Thumb2 decoder if they wanted to get nicer treatment of
the exiting 32-bit B/BLX instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2532
b42882b7-edfa-0310-969c-
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zwelch [Wed, 15 Jul 2009 23:39:48 +0000 (23:39 +0000)]
David Brownell <david-b@pacbell.net>:
Change layout of Thumb disassembly to work better with Thumb2:
- Move opcode to the left, allowing space for four hex bytes:
* after address, two spaces not one tab (taking 6 spaces)
* after 2-byte opcode, four spaces before tab
- Also, after opcode mnemonic use a tab not a space, to make
operands line up
Sample output (after some patches decoding a few 32-bit instructions):
0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000
0x00003e5e 0x601a STR r2, [r3, #0x0]
0x00003e60 0x2800 CMP r0, #0x00
0x00003e62 0xd1f3 BNE 0x00003e4c
0x00003e64 0xf008fa38 BL 0x0000c2d8
The affected lines of code now wrap at sane margins too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2531
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zwelch [Wed, 15 Jul 2009 23:39:37 +0000 (23:39 +0000)]
David Brownell <david-b@pacbell.net>:
Initial support for disassembling Thumb2 code. This works only for
Cortex-M3 cores so far. Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.
- Update the 16-bit Thumb decoder:
* Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
by ARMv6. (It already seems to treat CPY as MOV.)
* Understand CB, CBNZ, WFI, IT, and other opcodes added by
in Thumb2.
- A new Thumb2 instruction decode routine is provided.
* This has a different signature: pass the target, not the
instruction, so it can fetch a second halfword when needed.
The instruction size is likewise returned to the caller.
* 32-bit instructions are recognized but not yet decoded.
- Start using the current "UAL" syntax in some cases. "SWI" is
renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".
- Define a new "cortex_m3 disassemble addr count" command to give
access to this disassembly.
Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2530
b42882b7-edfa-0310-969c-
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| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)