1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
19 * GNU General public License for more details. *
21 * You should have received a copy of the GNU General public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ****************************************************************************/
27 /* Some of the the lower level code was based on code supplied by
28 * ATMEL under this copyright. */
30 /* BEGIN ATMEL COPYRIGHT */
31 /* ----------------------------------------------------------------------------
32 * ATMEL Microcontroller Software Support
33 * ----------------------------------------------------------------------------
34 * Copyright (c) 2009, Atmel Corporation
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
41 * - Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the disclaimer below.
44 * Atmel's name may not be used to endorse or promote products derived from
45 * this software without specific prior written permission.
47 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
50 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
53 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
56 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ----------------------------------------------------------------------------
59 /* END ATMEL COPYRIGHT */
66 #include <helper/time_support.h>
68 #define REG_NAME_WIDTH (12)
70 /* at91sam4s/at91sam4e series (has always one flash bank)*/
71 #define FLASH_BANK_BASE_S 0x00400000
73 /* at91sam4sd series (two one flash banks), first bank address */
74 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
75 /* at91sam4sd16x, second bank address */
76 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
77 /* at91sam4sd32x, second bank address */
78 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
80 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
81 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
82 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
83 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
84 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
85 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
86 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
87 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
88 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
103 extern struct flash_driver at91sam4_flash
;
105 static float _tomhz(uint32_t freq_hz
)
109 f
= ((float)(freq_hz
)) / 1000000.0;
113 /* How the chip is configured. */
115 uint32_t unique_id
[4];
119 uint32_t mainosc_freq
;
129 #define SAM4_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR
;
131 #define SAM4_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID
;
134 #define SAM4_PMC_BASE (0x400E0400)
135 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
137 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
139 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
141 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
143 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
145 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
147 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
149 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
151 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
153 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
155 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
157 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
159 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
161 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 struct sam4_bank_private
{
167 /* DANGER: THERE ARE DRAGONS HERE.. */
168 /* NOTE: If you add more 'ghost' pointers */
169 /* be aware that you must *manually* update */
170 /* these pointers in the function sam4_GetDetails() */
171 /* See the comment "Here there be dragons" */
173 /* so we can find the chip we belong to */
174 struct sam4_chip
*pChip
;
175 /* so we can find the original bank pointer */
176 struct flash_bank
*pBank
;
177 unsigned bank_number
;
178 uint32_t controller_address
;
179 uint32_t base_address
;
180 uint32_t flash_wait_states
;
184 unsigned sector_size
;
188 struct sam4_chip_details
{
189 /* THERE ARE DRAGONS HERE.. */
190 /* note: If you add pointers here */
191 /* be careful about them as they */
192 /* may need to be updated inside */
193 /* the function: "sam4_GetDetails() */
194 /* which copy/overwrites the */
195 /* 'runtime' copy of this structure */
196 uint32_t chipid_cidr
;
200 #define SAM4_N_NVM_BITS 3
201 unsigned gpnvm
[SAM4_N_NVM_BITS
];
202 unsigned total_flash_size
;
203 unsigned total_sram_size
;
205 #define SAM4_MAX_FLASH_BANKS 2
206 /* these are "initialized" from the global const data */
207 struct sam4_bank_private bank
[SAM4_MAX_FLASH_BANKS
];
211 struct sam4_chip
*next
;
214 /* this is "initialized" from the global const structure */
215 struct sam4_chip_details details
;
216 struct target
*target
;
221 struct sam4_reg_list
{
222 uint32_t address
; size_t struct_offset
; const char *name
;
223 void (*explain_func
)(struct sam4_chip
*pInfo
);
226 static struct sam4_chip
*all_sam4_chips
;
228 static struct sam4_chip
*get_current_sam4(struct command_context
*cmd_ctx
)
231 static struct sam4_chip
*p
;
233 t
= get_current_target(cmd_ctx
);
235 command_print(cmd_ctx
, "No current target?");
241 /* this should not happen */
242 /* the command is not registered until the chip is created? */
243 command_print(cmd_ctx
, "No SAM4 chips exist?");
252 command_print(cmd_ctx
, "Cannot find SAM4 chip?");
256 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
257 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
258 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
259 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
261 /* these are used to *initialize* the "pChip->details" structure. */
262 static const struct sam4_chip_details all_sam4_details
[] = {
264 /* Start at91sam4e* series */
265 /*atsam4e16e - LQFP144/LFBGA144*/
267 .chipid_cidr
= 0xA3CC0CE0,
268 .name
= "at91sam4e16e",
269 .total_flash_size
= 1024 * 1024,
270 .total_sram_size
= 128 * 1024,
280 .base_address
= FLASH_BANK_BASE_S
,
281 .controller_address
= 0x400e0a00,
282 .flash_wait_states
= 6, /* workaround silicon bug */
284 .size_bytes
= 1024 * 1024,
299 /* Start at91sam4s* series */
300 /*atsam4s16c - LQFP100/BGA100*/
302 .chipid_cidr
= 0x28AC0CE0,
303 .name
= "at91sam4s16c",
304 .total_flash_size
= 1024 * 1024,
305 .total_sram_size
= 128 * 1024,
315 .base_address
= FLASH_BANK_BASE_S
,
316 .controller_address
= 0x400e0a00,
317 .flash_wait_states
= 6, /* workaround silicon bug */
319 .size_bytes
= 1024 * 1024,
333 /*atsam4s16b - LQFP64/QFN64*/
335 .chipid_cidr
= 0x289C0CE0,
336 .name
= "at91sam4s16b",
337 .total_flash_size
= 1024 * 1024,
338 .total_sram_size
= 128 * 1024,
348 .base_address
= FLASH_BANK_BASE_S
,
349 .controller_address
= 0x400e0a00,
350 .flash_wait_states
= 6, /* workaround silicon bug */
352 .size_bytes
= 1024 * 1024,
366 /*atsam4s16a - LQFP48/QFN48*/
368 .chipid_cidr
= 0x288C0CE0,
369 .name
= "at91sam4s16a",
370 .total_flash_size
= 1024 * 1024,
371 .total_sram_size
= 128 * 1024,
381 .base_address
= FLASH_BANK_BASE_S
,
382 .controller_address
= 0x400e0a00,
383 .flash_wait_states
= 6, /* workaround silicon bug */
385 .size_bytes
= 1024 * 1024,
399 /*atsam4s8c - LQFP100/BGA100*/
401 .chipid_cidr
= 0x28AC0AE0,
402 .name
= "at91sam4s8c",
403 .total_flash_size
= 512 * 1024,
404 .total_sram_size
= 128 * 1024,
414 .base_address
= FLASH_BANK_BASE_S
,
415 .controller_address
= 0x400e0a00,
416 .flash_wait_states
= 6, /* workaround silicon bug */
418 .size_bytes
= 512 * 1024,
432 /*atsam4s8b - LQFP64/BGA64*/
434 .chipid_cidr
= 0x289C0AE0,
435 .name
= "at91sam4s8b",
436 .total_flash_size
= 512 * 1024,
437 .total_sram_size
= 128 * 1024,
447 .base_address
= FLASH_BANK_BASE_S
,
448 .controller_address
= 0x400e0a00,
449 .flash_wait_states
= 6, /* workaround silicon bug */
451 .size_bytes
= 512 * 1024,
465 /*atsam4s8a - LQFP48/BGA48*/
467 .chipid_cidr
= 0x288C0AE0,
468 .name
= "at91sam4s8a",
469 .total_flash_size
= 512 * 1024,
470 .total_sram_size
= 128 * 1024,
480 .base_address
= FLASH_BANK_BASE_S
,
481 .controller_address
= 0x400e0a00,
482 .flash_wait_states
= 6, /* workaround silicon bug */
484 .size_bytes
= 512 * 1024,
499 /*atsam4s4a - LQFP48/BGA48*/
501 .chipid_cidr
= 0x288b09e0,
502 .name
= "at91sam4s4a",
503 .total_flash_size
= 256 * 1024,
504 .total_sram_size
= 64 * 1024,
514 .base_address
= FLASH_BANK_BASE_S
,
515 .controller_address
= 0x400e0a00,
516 .flash_wait_states
= 6, /* workaround silicon bug */
518 .size_bytes
= 256 * 1024,
535 .chipid_cidr
= 0x29a70ee0,
536 .name
= "at91sam4sd32c",
537 .total_flash_size
= 2048 * 1024,
538 .total_sram_size
= 160 * 1024,
549 .base_address
= FLASH_BANK0_BASE_SD
,
550 .controller_address
= 0x400e0a00,
551 .flash_wait_states
= 6, /* workaround silicon bug */
553 .size_bytes
= 1024 * 1024,
565 .base_address
= FLASH_BANK1_BASE_2048K_SD
,
566 .controller_address
= 0x400e0c00,
567 .flash_wait_states
= 6, /* workaround silicon bug */
569 .size_bytes
= 1024 * 1024,
579 .chipid_cidr
= 0x29a70ce0,
580 .name
= "at91sam4sd16c",
581 .total_flash_size
= 1024 * 1024,
582 .total_sram_size
= 160 * 1024,
593 .base_address
= FLASH_BANK0_BASE_SD
,
594 .controller_address
= 0x400e0a00,
595 .flash_wait_states
= 6, /* workaround silicon bug */
597 .size_bytes
= 512 * 1024,
609 .base_address
= FLASH_BANK1_BASE_1024K_SD
,
610 .controller_address
= 0x400e0c00,
611 .flash_wait_states
= 6, /* workaround silicon bug */
613 .size_bytes
= 512 * 1024,
623 .chipid_cidr
= 0x28a70ce0,
624 .name
= "at91sam4sa16c",
625 .total_flash_size
= 1024 * 1024,
626 .total_sram_size
= 160 * 1024,
637 .base_address
= FLASH_BANK0_BASE_SD
,
638 .controller_address
= 0x400e0a00,
639 .flash_wait_states
= 6, /* workaround silicon bug */
641 .size_bytes
= 512 * 1024,
653 .base_address
= FLASH_BANK1_BASE_1024K_SD
,
654 .controller_address
= 0x400e0c00,
655 .flash_wait_states
= 6, /* workaround silicon bug */
657 .size_bytes
= 512 * 1024,
667 .chipid_cidr
= 0x247e0ae0,
668 .name
= "at91samg53n19",
669 .total_flash_size
= 512 * 1024,
670 .total_sram_size
= 96 * 1024,
681 .base_address
= FLASH_BANK_BASE_S
,
682 .controller_address
= 0x400e0a00,
683 .flash_wait_states
= 6, /* workaround silicon bug */
685 .size_bytes
= 512 * 1024,
708 /***********************************************************************
709 **********************************************************************
710 **********************************************************************
711 **********************************************************************
712 **********************************************************************
713 **********************************************************************/
714 /* *ATMEL* style code - from the SAM4 driver code */
717 * Get the current status of the EEFC and
718 * the value of some status bits (LOCKE, PROGE).
719 * @param pPrivate - info about the bank
720 * @param v - result goes here
722 static int EFC_GetStatus(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
725 r
= target_read_u32(pPrivate
->pChip
->target
,
726 pPrivate
->controller_address
+ offset_EFC_FSR
,
728 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
730 ((unsigned int)((*v
>> 2) & 1)),
731 ((unsigned int)((*v
>> 1) & 1)),
732 ((unsigned int)((*v
>> 0) & 1)));
738 * Get the result of the last executed command.
739 * @param pPrivate - info about the bank
740 * @param v - result goes here
742 static int EFC_GetResult(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
746 r
= target_read_u32(pPrivate
->pChip
->target
,
747 pPrivate
->controller_address
+ offset_EFC_FRR
,
751 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
755 static int EFC_StartCommand(struct sam4_bank_private
*pPrivate
,
756 unsigned command
, unsigned argument
)
765 /* Check command & argument */
768 case AT91C_EFC_FCMD_WP
:
769 case AT91C_EFC_FCMD_WPL
:
770 case AT91C_EFC_FCMD_EWP
:
771 case AT91C_EFC_FCMD_EWPL
:
772 /* case AT91C_EFC_FCMD_EPL: */
773 case AT91C_EFC_FCMD_EPA
:
774 case AT91C_EFC_FCMD_SLB
:
775 case AT91C_EFC_FCMD_CLB
:
776 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
778 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
781 case AT91C_EFC_FCMD_SFB
:
782 case AT91C_EFC_FCMD_CFB
:
783 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
784 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
785 pPrivate
->pChip
->details
.n_gpnvms
);
789 case AT91C_EFC_FCMD_GETD
:
790 case AT91C_EFC_FCMD_EA
:
791 case AT91C_EFC_FCMD_GLB
:
792 case AT91C_EFC_FCMD_GFB
:
793 case AT91C_EFC_FCMD_STUI
:
794 case AT91C_EFC_FCMD_SPUI
:
796 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
799 LOG_ERROR("Unknown command %d", command
);
803 if (command
== AT91C_EFC_FCMD_SPUI
) {
804 /* this is a very special situation. */
805 /* Situation (1) - error/retry - see below */
806 /* And we are being called recursively */
807 /* Situation (2) - normal, finished reading unique id */
809 /* it should be "ready" */
810 EFC_GetStatus(pPrivate
, &v
);
812 /* then it is ready */
816 /* we have done this before */
817 /* the controller is not responding. */
818 LOG_ERROR("flash controller(%d) is not ready! Error",
819 pPrivate
->bank_number
);
823 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
824 pPrivate
->bank_number
);
825 /* we do that by issuing the *STOP* command */
826 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
827 /* above is recursive, and further recursion is blocked by */
828 /* if (command == AT91C_EFC_FCMD_SPUI) above */
834 v
= (0x5A << 24) | (argument
<< 8) | command
;
835 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
836 r
= target_write_u32(pPrivate
->pBank
->target
,
837 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
839 LOG_DEBUG("Error Write failed");
844 * Performs the given command and wait until its completion (or an error).
845 * @param pPrivate - info about the bank
846 * @param command - Command to perform.
847 * @param argument - Optional command argument.
848 * @param status - put command status bits here
850 static int EFC_PerformCommand(struct sam4_bank_private
*pPrivate
,
858 long long ms_now
, ms_end
;
864 r
= EFC_StartCommand(pPrivate
, command
, argument
);
868 ms_end
= 10000 + timeval_ms();
871 r
= EFC_GetStatus(pPrivate
, &v
);
874 ms_now
= timeval_ms();
875 if (ms_now
> ms_end
) {
877 LOG_ERROR("Command timeout");
880 } while ((v
& 1) == 0);
890 * Read the unique ID.
891 * @param pPrivate - info about the bank
892 * The unique ID is stored in the 'pPrivate' structure.
894 static int FLASHD_ReadUniqueID(struct sam4_bank_private
*pPrivate
)
900 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
901 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
902 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
903 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
906 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
910 for (x
= 0; x
< 4; x
++) {
911 r
= target_read_u32(pPrivate
->pChip
->target
,
912 pPrivate
->pBank
->base
+ (x
* 4),
916 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
919 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
920 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
922 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
923 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
924 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
925 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
931 * Erases the entire flash.
932 * @param pPrivate - the info about the bank.
934 static int FLASHD_EraseEntireBank(struct sam4_bank_private
*pPrivate
)
937 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
941 * Erases the entire flash.
942 * @param pPrivate - the info about the bank.
944 static int FLASHD_ErasePages(struct sam4_bank_private
*pPrivate
,
969 /* AT91C_EFC_FCMD_EPA
970 * According to the datasheet FARG[15:2] defines the page from which
971 * the erase will start.This page must be modulo 4, 8, 16 or 32
972 * according to the number of pages to erase. FARG[1:0] defines the
973 * number of pages to be erased. Previously (firstpage << 2) was used
974 * to conform to this, seems it should not be shifted...
976 return EFC_PerformCommand(pPrivate
,
977 /* send Erase Page */
979 (firstPage
) | erasePages
,
984 * Gets current GPNVM state.
985 * @param pPrivate - info about the bank.
986 * @param gpnvm - GPNVM bit index.
987 * @param puthere - result stored here.
989 /* ------------------------------------------------------------------------------ */
990 static int FLASHD_GetGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
996 if (pPrivate
->bank_number
!= 0) {
997 LOG_ERROR("GPNVM only works with Bank0");
1001 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1002 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1003 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1007 /* Get GPNVMs status */
1008 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1009 if (r
!= ERROR_OK
) {
1010 LOG_ERROR("Failed");
1014 r
= EFC_GetResult(pPrivate
, &v
);
1017 /* Check if GPNVM is set */
1018 /* get the bit and make it a 0/1 */
1019 *puthere
= (v
>> gpnvm
) & 1;
1026 * Clears the selected GPNVM bit.
1027 * @param pPrivate info about the bank
1028 * @param gpnvm GPNVM index.
1029 * @returns 0 if successful; otherwise returns an error code.
1031 static int FLASHD_ClrGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
)
1037 if (pPrivate
->bank_number
!= 0) {
1038 LOG_ERROR("GPNVM only works with Bank0");
1042 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1043 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1044 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1048 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1049 if (r
!= ERROR_OK
) {
1050 LOG_DEBUG("Failed: %d", r
);
1053 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1054 LOG_DEBUG("End: %d", r
);
1059 * Sets the selected GPNVM bit.
1060 * @param pPrivate info about the bank
1061 * @param gpnvm GPNVM index.
1063 static int FLASHD_SetGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
)
1068 if (pPrivate
->bank_number
!= 0) {
1069 LOG_ERROR("GPNVM only works with Bank0");
1073 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1074 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1075 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1079 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1087 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1093 * Returns a bit field (at most 64) of locked regions within a page.
1094 * @param pPrivate info about the bank
1095 * @param v where to store locked bits
1097 static int FLASHD_GetLockBits(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
1101 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1102 if (r
== ERROR_OK
) {
1103 EFC_GetResult(pPrivate
, v
);
1104 EFC_GetResult(pPrivate
, v
);
1105 EFC_GetResult(pPrivate
, v
);
1106 r
= EFC_GetResult(pPrivate
, v
);
1108 LOG_DEBUG("End: %d", r
);
1113 * Unlocks all the regions in the given address range.
1114 * @param pPrivate info about the bank
1115 * @param start_sector first sector to unlock
1116 * @param end_sector last (inclusive) to unlock
1119 static int FLASHD_Unlock(struct sam4_bank_private
*pPrivate
,
1120 unsigned start_sector
,
1121 unsigned end_sector
)
1126 uint32_t pages_per_sector
;
1128 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1130 /* Unlock all pages */
1131 while (start_sector
<= end_sector
) {
1132 pg
= start_sector
* pages_per_sector
;
1134 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1145 * @param pPrivate - info about the bank
1146 * @param start_sector - first sector to lock
1147 * @param end_sector - last sector (inclusive) to lock
1149 static int FLASHD_Lock(struct sam4_bank_private
*pPrivate
,
1150 unsigned start_sector
,
1151 unsigned end_sector
)
1155 uint32_t pages_per_sector
;
1158 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1160 /* Lock all pages */
1161 while (start_sector
<= end_sector
) {
1162 pg
= start_sector
* pages_per_sector
;
1164 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1172 /****** END SAM4 CODE ********/
1174 /* begin helpful debug code */
1175 /* print the fieldname, the field value, in dec & hex, and return field value */
1176 static uint32_t sam4_reg_fieldname(struct sam4_chip
*pChip
,
1177 const char *regname
,
1186 /* extract the field */
1188 v
= v
& ((1 << width
)-1);
1197 /* show the basics */
1198 LOG_USER_N("\t%*s: %*" PRId32
" [0x%0*" PRIx32
"] ",
1199 REG_NAME_WIDTH
, regname
,
1205 static const char _unknown
[] = "unknown";
1206 static const char *const eproc_names
[] = {
1210 "cortex-m3", /* 3 */
1212 "arm926ejs", /* 5 */
1213 "cortex-a5", /* 6 */
1214 "cortex-m4", /* 7 */
1225 #define nvpsize2 nvpsize /* these two tables are identical */
1226 static const char *const nvpsize
[] = {
1229 "16K bytes", /* 2 */
1230 "32K bytes", /* 3 */
1232 "64K bytes", /* 5 */
1234 "128K bytes", /* 7 */
1236 "256K bytes", /* 9 */
1237 "512K bytes", /* 10 */
1239 "1024K bytes", /* 12 */
1241 "2048K bytes", /* 14 */
1245 static const char *const sramsize
[] = {
1246 "48K Bytes", /* 0 */
1250 "112K Bytes", /* 4 */
1252 "80K Bytes", /* 6 */
1253 "160K Bytes", /* 7 */
1255 "16K Bytes", /* 9 */
1256 "32K Bytes", /* 10 */
1257 "64K Bytes", /* 11 */
1258 "128K Bytes", /* 12 */
1259 "256K Bytes", /* 13 */
1260 "96K Bytes", /* 14 */
1261 "512K Bytes", /* 15 */
1265 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1266 { 0x19, "AT91SAM9xx Series" },
1267 { 0x29, "AT91SAM9XExx Series" },
1268 { 0x34, "AT91x34 Series" },
1269 { 0x37, "CAP7 Series" },
1270 { 0x39, "CAP9 Series" },
1271 { 0x3B, "CAP11 Series" },
1272 { 0x3C, "ATSAM4E" },
1273 { 0x40, "AT91x40 Series" },
1274 { 0x42, "AT91x42 Series" },
1275 { 0x43, "SAMG51 Series"
1277 { 0x47, "SAMG53 Series"
1279 { 0x55, "AT91x55 Series" },
1280 { 0x60, "AT91SAM7Axx Series" },
1281 { 0x61, "AT91SAM7AQxx Series" },
1282 { 0x63, "AT91x63 Series" },
1283 { 0x70, "AT91SAM7Sxx Series" },
1284 { 0x71, "AT91SAM7XCxx Series" },
1285 { 0x72, "AT91SAM7SExx Series" },
1286 { 0x73, "AT91SAM7Lxx Series" },
1287 { 0x75, "AT91SAM7Xxx Series" },
1288 { 0x76, "AT91SAM7SLxx Series" },
1289 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1290 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1291 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1292 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1293 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1294 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1295 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1296 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1297 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1298 { 0x92, "AT91x92 Series" },
1299 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1300 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1301 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1302 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1303 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1304 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1305 { 0xA5, "ATSAM5A" },
1306 { 0xF0, "AT75Cxx Series" },
1310 static const char *const nvptype
[] = {
1312 "romless or onchip flash", /* 1 */
1313 "embedded flash memory",/* 2 */
1314 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1315 "sram emulating flash", /* 4 */
1321 static const char *_yes_or_no(uint32_t v
)
1329 static const char *const _rc_freq
[] = {
1330 "4 MHz", "8 MHz", "12 MHz", "reserved"
1333 static void sam4_explain_ckgr_mor(struct sam4_chip
*pChip
)
1338 v
= sam4_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1339 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
1340 v
= sam4_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1341 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
1342 rcen
= sam4_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
1343 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
1344 v
= sam4_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1345 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
1347 pChip
->cfg
.rc_freq
= 0;
1351 pChip
->cfg
.rc_freq
= 0;
1354 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1357 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1360 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
1365 v
= sam4_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1366 LOG_USER("(startup clks, time= %f uSecs)",
1367 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1368 v
= sam4_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1369 LOG_USER("(mainosc source: %s)",
1370 v
? "external xtal" : "internal RC");
1372 v
= sam4_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1373 LOG_USER("(clock failure enabled: %s)",
1377 static void sam4_explain_chipid_cidr(struct sam4_chip
*pChip
)
1383 sam4_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1386 v
= sam4_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1387 LOG_USER("%s", eproc_names
[v
]);
1389 v
= sam4_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1390 LOG_USER("%s", nvpsize
[v
]);
1392 v
= sam4_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1393 LOG_USER("%s", nvpsize2
[v
]);
1395 v
= sam4_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
1396 LOG_USER("%s", sramsize
[v
]);
1398 v
= sam4_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1400 for (x
= 0; archnames
[x
].name
; x
++) {
1401 if (v
== archnames
[x
].value
) {
1402 cp
= archnames
[x
].name
;
1409 v
= sam4_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
1410 LOG_USER("%s", nvptype
[v
]);
1412 v
= sam4_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
1413 LOG_USER("(exists: %s)", _yes_or_no(v
));
1416 static void sam4_explain_ckgr_mcfr(struct sam4_chip
*pChip
)
1420 v
= sam4_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
1421 LOG_USER("(main ready: %s)", _yes_or_no(v
));
1423 v
= sam4_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
1425 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1426 pChip
->cfg
.mainosc_freq
= v
;
1428 LOG_USER("(%3.03f Mhz (%" PRIu32
".%03" PRIu32
"khz slowclk)",
1430 (uint32_t)(pChip
->cfg
.slow_freq
/ 1000),
1431 (uint32_t)(pChip
->cfg
.slow_freq
% 1000));
1434 static void sam4_explain_ckgr_plla(struct sam4_chip
*pChip
)
1436 uint32_t mula
, diva
;
1438 diva
= sam4_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
1440 mula
= sam4_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
1442 pChip
->cfg
.plla_freq
= 0;
1444 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1446 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1447 else if (diva
>= 1) {
1448 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
1449 LOG_USER("\tPLLA Freq: %3.03f MHz",
1450 _tomhz(pChip
->cfg
.plla_freq
));
1454 static void sam4_explain_mckr(struct sam4_chip
*pChip
)
1456 uint32_t css
, pres
, fin
= 0;
1458 const char *cp
= NULL
;
1460 css
= sam4_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
1463 fin
= pChip
->cfg
.slow_freq
;
1467 fin
= pChip
->cfg
.mainosc_freq
;
1471 fin
= pChip
->cfg
.plla_freq
;
1475 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
1476 fin
= 480 * 1000 * 1000;
1480 cp
= "upll (*ERROR* UPLL is disabled)";
1488 LOG_USER("%s (%3.03f Mhz)",
1491 pres
= sam4_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
1492 switch (pres
& 0x07) {
1495 cp
= "selected clock";
1529 LOG_USER("(%s)", cp
);
1531 /* sam4 has a *SINGLE* clock - */
1532 /* other at91 series parts have divisors for these. */
1533 pChip
->cfg
.cpu_freq
= fin
;
1534 pChip
->cfg
.mclk_freq
= fin
;
1535 pChip
->cfg
.fclk_freq
= fin
;
1536 LOG_USER("\t\tResult CPU Freq: %3.03f",
1541 static struct sam4_chip
*target2sam4(struct target
*pTarget
)
1543 struct sam4_chip
*pChip
;
1545 if (pTarget
== NULL
)
1548 pChip
= all_sam4_chips
;
1550 if (pChip
->target
== pTarget
)
1551 break; /* return below */
1553 pChip
= pChip
->next
;
1559 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg
*pCfg
, const struct sam4_reg_list
*pList
)
1561 /* this function exists to help */
1562 /* keep funky offsetof() errors */
1563 /* and casting from causing bugs */
1565 /* By using prototypes - we can detect what would */
1566 /* be casting errors. */
1568 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
1572 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
1574 NAME), # NAME, FUNC }
1575 static const struct sam4_reg_list sam4_all_regs
[] = {
1576 SAM4_ENTRY(CKGR_MOR
, sam4_explain_ckgr_mor
),
1577 SAM4_ENTRY(CKGR_MCFR
, sam4_explain_ckgr_mcfr
),
1578 SAM4_ENTRY(CKGR_PLLAR
, sam4_explain_ckgr_plla
),
1579 SAM4_ENTRY(CKGR_UCKR
, NULL
),
1580 SAM4_ENTRY(PMC_FSMR
, NULL
),
1581 SAM4_ENTRY(PMC_FSPR
, NULL
),
1582 SAM4_ENTRY(PMC_IMR
, NULL
),
1583 SAM4_ENTRY(PMC_MCKR
, sam4_explain_mckr
),
1584 SAM4_ENTRY(PMC_PCK0
, NULL
),
1585 SAM4_ENTRY(PMC_PCK1
, NULL
),
1586 SAM4_ENTRY(PMC_PCK2
, NULL
),
1587 SAM4_ENTRY(PMC_PCSR
, NULL
),
1588 SAM4_ENTRY(PMC_SCSR
, NULL
),
1589 SAM4_ENTRY(PMC_SR
, NULL
),
1590 SAM4_ENTRY(CHIPID_CIDR
, sam4_explain_chipid_cidr
),
1591 SAM4_ENTRY(CHIPID_EXID
, NULL
),
1592 /* TERMINATE THE LIST */
1597 static struct sam4_bank_private
*get_sam4_bank_private(struct flash_bank
*bank
)
1599 return bank
->driver_priv
;
1603 * Given a pointer to where it goes in the structure,
1604 * determine the register name, address from the all registers table.
1606 static const struct sam4_reg_list
*sam4_GetReg(struct sam4_chip
*pChip
, uint32_t *goes_here
)
1608 const struct sam4_reg_list
*pReg
;
1610 pReg
= &(sam4_all_regs
[0]);
1611 while (pReg
->name
) {
1612 uint32_t *pPossible
;
1614 /* calculate where this one go.. */
1615 /* it is "possibly" this register. */
1617 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
1619 /* well? Is it this register */
1620 if (pPossible
== goes_here
) {
1628 /* This is *TOTAL*PANIC* - we are totally screwed. */
1629 LOG_ERROR("INVALID SAM4 REGISTER");
1633 static int sam4_ReadThisReg(struct sam4_chip
*pChip
, uint32_t *goes_here
)
1635 const struct sam4_reg_list
*pReg
;
1638 pReg
= sam4_GetReg(pChip
, goes_here
);
1642 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
1643 if (r
!= ERROR_OK
) {
1644 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
1645 pReg
->name
, (unsigned)(pReg
->address
), r
);
1650 static int sam4_ReadAllRegs(struct sam4_chip
*pChip
)
1653 const struct sam4_reg_list
*pReg
;
1655 pReg
= &(sam4_all_regs
[0]);
1656 while (pReg
->name
) {
1657 r
= sam4_ReadThisReg(pChip
,
1658 sam4_get_reg_ptr(&(pChip
->cfg
), pReg
));
1659 if (r
!= ERROR_OK
) {
1660 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
1661 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
1670 static int sam4_GetInfo(struct sam4_chip
*pChip
)
1672 const struct sam4_reg_list
*pReg
;
1675 pReg
= &(sam4_all_regs
[0]);
1676 while (pReg
->name
) {
1677 /* display all regs */
1678 LOG_DEBUG("Start: %s", pReg
->name
);
1679 regval
= *sam4_get_reg_ptr(&(pChip
->cfg
), pReg
);
1680 LOG_USER("%*s: [0x%08" PRIx32
"] -> 0x%08" PRIx32
,
1685 if (pReg
->explain_func
)
1686 (*(pReg
->explain_func
))(pChip
);
1687 LOG_DEBUG("End: %s", pReg
->name
);
1690 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
1691 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
1692 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
1693 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
1694 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
1696 LOG_USER(" UniqueId: 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08"PRIx32
,
1697 pChip
->cfg
.unique_id
[0],
1698 pChip
->cfg
.unique_id
[1],
1699 pChip
->cfg
.unique_id
[2],
1700 pChip
->cfg
.unique_id
[3]);
1705 static int sam4_protect_check(struct flash_bank
*bank
)
1708 uint32_t v
[4] = {0};
1710 struct sam4_bank_private
*pPrivate
;
1713 if (bank
->target
->state
!= TARGET_HALTED
) {
1714 LOG_ERROR("Target not halted");
1715 return ERROR_TARGET_NOT_HALTED
;
1718 pPrivate
= get_sam4_bank_private(bank
);
1720 LOG_ERROR("no private for this bank?");
1723 if (!(pPrivate
->probed
))
1724 return ERROR_FLASH_BANK_NOT_PROBED
;
1726 r
= FLASHD_GetLockBits(pPrivate
, v
);
1727 if (r
!= ERROR_OK
) {
1728 LOG_DEBUG("Failed: %d", r
);
1732 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
1733 bank
->sectors
[x
].is_protected
= (!!(v
[x
>> 5] & (1 << (x
% 32))));
1738 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command
)
1740 struct sam4_chip
*pChip
;
1742 pChip
= all_sam4_chips
;
1744 /* is this an existing chip? */
1746 if (pChip
->target
== bank
->target
)
1748 pChip
= pChip
->next
;
1752 /* this is a *NEW* chip */
1753 pChip
= calloc(1, sizeof(struct sam4_chip
));
1755 LOG_ERROR("NO RAM!");
1758 pChip
->target
= bank
->target
;
1759 /* insert at head */
1760 pChip
->next
= all_sam4_chips
;
1761 all_sam4_chips
= pChip
;
1762 pChip
->target
= bank
->target
;
1763 /* assumption is this runs at 32khz */
1764 pChip
->cfg
.slow_freq
= 32768;
1768 switch (bank
->base
) {
1770 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
1771 "[at91sam4s series] )",
1772 ((unsigned int)(bank
->base
)),
1773 ((unsigned int)(FLASH_BANK_BASE_S
)));
1777 /* at91sam4s series only has bank 0*/
1778 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
1779 case FLASH_BANK_BASE_S
:
1780 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1781 bank
->bank_number
= 0;
1782 pChip
->details
.bank
[0].pChip
= pChip
;
1783 pChip
->details
.bank
[0].pBank
= bank
;
1786 /* Bank 1 of at91sam4sd series */
1787 case FLASH_BANK1_BASE_1024K_SD
:
1788 case FLASH_BANK1_BASE_2048K_SD
:
1789 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
1790 bank
->bank_number
= 1;
1791 pChip
->details
.bank
[1].pChip
= pChip
;
1792 pChip
->details
.bank
[1].pBank
= bank
;
1796 /* we initialize after probing. */
1800 static int sam4_GetDetails(struct sam4_bank_private
*pPrivate
)
1802 const struct sam4_chip_details
*pDetails
;
1803 struct sam4_chip
*pChip
;
1804 struct flash_bank
*saved_banks
[SAM4_MAX_FLASH_BANKS
];
1808 pDetails
= all_sam4_details
;
1809 while (pDetails
->name
) {
1810 /* Compare cidr without version bits */
1811 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
1816 if (pDetails
->name
== NULL
) {
1817 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
1818 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
1819 /* Help the victim, print details about the chip */
1820 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32
" decodes as follows",
1821 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
1822 sam4_explain_chipid_cidr(pPrivate
->pChip
);
1826 /* DANGER: THERE ARE DRAGONS HERE */
1828 /* get our pChip - it is going */
1829 /* to be over-written shortly */
1830 pChip
= pPrivate
->pChip
;
1832 /* Note that, in reality: */
1834 /* pPrivate = &(pChip->details.bank[0]) */
1835 /* or pPrivate = &(pChip->details.bank[1]) */
1838 /* save the "bank" pointers */
1839 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++)
1840 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
1842 /* Overwrite the "details" structure. */
1843 memcpy(&(pPrivate
->pChip
->details
),
1845 sizeof(pPrivate
->pChip
->details
));
1847 /* now fix the ghosted pointers */
1848 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
1849 pChip
->details
.bank
[x
].pChip
= pChip
;
1850 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
1853 /* update the *BANK*SIZE* */
1859 static int _sam4_probe(struct flash_bank
*bank
, int noise
)
1863 struct sam4_bank_private
*pPrivate
;
1866 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
1867 if (bank
->target
->state
!= TARGET_HALTED
) {
1868 LOG_ERROR("Target not halted");
1869 return ERROR_TARGET_NOT_HALTED
;
1872 pPrivate
= get_sam4_bank_private(bank
);
1874 LOG_ERROR("Invalid/unknown bank number");
1878 r
= sam4_ReadAllRegs(pPrivate
->pChip
);
1883 if (pPrivate
->pChip
->probed
)
1884 r
= sam4_GetInfo(pPrivate
->pChip
);
1886 r
= sam4_GetDetails(pPrivate
);
1890 /* update the flash bank size */
1891 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
1892 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
1893 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
1898 if (bank
->sectors
== NULL
) {
1899 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
1900 if (bank
->sectors
== NULL
) {
1901 LOG_ERROR("No memory!");
1904 bank
->num_sectors
= pPrivate
->nsectors
;
1906 for (x
= 0; ((int)(x
)) < bank
->num_sectors
; x
++) {
1907 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
1908 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
1909 /* mark as unknown */
1910 bank
->sectors
[x
].is_erased
= -1;
1911 bank
->sectors
[x
].is_protected
= -1;
1915 pPrivate
->probed
= 1;
1917 r
= sam4_protect_check(bank
);
1921 LOG_DEBUG("Bank = %d, nbanks = %d",
1922 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
1923 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
1924 /* read unique id, */
1925 /* it appears to be associated with the *last* flash bank. */
1926 FLASHD_ReadUniqueID(pPrivate
);
1932 static int sam4_probe(struct flash_bank
*bank
)
1934 return _sam4_probe(bank
, 1);
1937 static int sam4_auto_probe(struct flash_bank
*bank
)
1939 return _sam4_probe(bank
, 0);
1942 static int sam4_erase(struct flash_bank
*bank
, int first
, int last
)
1944 struct sam4_bank_private
*pPrivate
;
1948 /*16 pages equals 8KB - Same size as a lock region*/
1953 if (bank
->target
->state
!= TARGET_HALTED
) {
1954 LOG_ERROR("Target not halted");
1955 return ERROR_TARGET_NOT_HALTED
;
1958 r
= sam4_auto_probe(bank
);
1959 if (r
!= ERROR_OK
) {
1960 LOG_DEBUG("Here,r=%d", r
);
1964 pPrivate
= get_sam4_bank_private(bank
);
1965 if (!(pPrivate
->probed
))
1966 return ERROR_FLASH_BANK_NOT_PROBED
;
1968 if ((first
== 0) && ((last
+ 1) == ((int)(pPrivate
->nsectors
)))) {
1971 return FLASHD_EraseEntireBank(pPrivate
);
1973 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
1974 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first
), (unsigned int)(last
));
1975 for (i
= first
; i
<= last
; i
++) {
1976 /*16 pages equals 8KB - Same size as a lock region*/
1977 r
= FLASHD_ErasePages(pPrivate
, (i
* pageCount
), pageCount
, &status
);
1978 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i
));
1980 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
1982 if (status
& (1 << 2)) {
1983 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i
));
1986 if (status
& (1 << 1)) {
1987 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i
));
1995 static int sam4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1997 struct sam4_bank_private
*pPrivate
;
2001 if (bank
->target
->state
!= TARGET_HALTED
) {
2002 LOG_ERROR("Target not halted");
2003 return ERROR_TARGET_NOT_HALTED
;
2006 pPrivate
= get_sam4_bank_private(bank
);
2007 if (!(pPrivate
->probed
))
2008 return ERROR_FLASH_BANK_NOT_PROBED
;
2011 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2013 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2014 LOG_DEBUG("End: r=%d", r
);
2020 static int sam4_page_read(struct sam4_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2025 adr
= pagenum
* pPrivate
->page_size
;
2026 adr
= adr
+ pPrivate
->base_address
;
2028 r
= target_read_memory(pPrivate
->pChip
->target
,
2030 4, /* THIS*MUST*BE* in 32bit values */
2031 pPrivate
->page_size
/ 4,
2034 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2035 (unsigned int)(adr
));
2039 static int sam4_page_write(struct sam4_bank_private
*pPrivate
, unsigned pagenum
, const uint8_t *buf
)
2043 uint32_t fmr
; /* EEFC Flash Mode Register */
2046 adr
= pagenum
* pPrivate
->page_size
;
2047 adr
= (adr
+ pPrivate
->base_address
);
2049 /* Get flash mode register value */
2050 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
2052 LOG_DEBUG("Error Read failed: read flash mode register");
2054 /* Clear flash wait state field */
2057 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2058 fmr
|= (pPrivate
->flash_wait_states
<< 8);
2060 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
2061 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
2063 LOG_DEBUG("Error Write failed: set flash mode register");
2065 /* 1st sector 8kBytes - page 0 - 15*/
2066 /* 2nd sector 8kBytes - page 16 - 30*/
2067 /* 3rd sector 48kBytes - page 31 - 127*/
2068 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2069 r
= target_write_memory(pPrivate
->pChip
->target
,
2071 4, /* THIS*MUST*BE* in 32bit values */
2072 pPrivate
->page_size
/ 4,
2074 if (r
!= ERROR_OK
) {
2075 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2076 (unsigned int)(adr
));
2080 r
= EFC_PerformCommand(pPrivate
,
2081 /* send Erase & Write Page */
2082 AT91C_EFC_FCMD_WP
, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2087 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2088 (unsigned int)(adr
));
2089 if (status
& (1 << 2)) {
2090 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2093 if (status
& (1 << 1)) {
2094 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2100 static int sam4_write(struct flash_bank
*bank
,
2101 const uint8_t *buffer
,
2109 unsigned page_offset
;
2110 struct sam4_bank_private
*pPrivate
;
2111 uint8_t *pagebuffer
;
2113 /* incase we bail further below, set this to null */
2116 /* ignore dumb requests */
2122 if (bank
->target
->state
!= TARGET_HALTED
) {
2123 LOG_ERROR("Target not halted");
2124 r
= ERROR_TARGET_NOT_HALTED
;
2128 pPrivate
= get_sam4_bank_private(bank
);
2129 if (!(pPrivate
->probed
)) {
2130 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2134 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2135 LOG_ERROR("Flash write error - past end of bank");
2136 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2137 (unsigned int)(offset
),
2138 (unsigned int)(count
),
2139 (unsigned int)(pPrivate
->size_bytes
));
2144 pagebuffer
= malloc(pPrivate
->page_size
);
2146 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2151 /* what page do we start & end in? */
2152 page_cur
= offset
/ pPrivate
->page_size
;
2153 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2155 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2156 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2158 /* Special case: all one page */
2161 /* (1) non-aligned start */
2162 /* (2) body pages */
2163 /* (3) non-aligned end. */
2165 /* Handle special case - all one page. */
2166 if (page_cur
== page_end
) {
2167 LOG_DEBUG("Special case, all in one page");
2168 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
2172 page_offset
= (offset
& (pPrivate
->page_size
-1));
2173 memcpy(pagebuffer
+ page_offset
,
2177 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
2184 /* non-aligned start */
2185 page_offset
= offset
& (pPrivate
->page_size
- 1);
2187 LOG_DEBUG("Not-Aligned start");
2188 /* read the partial */
2189 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
2193 /* over-write with new data */
2194 n
= (pPrivate
->page_size
- page_offset
);
2195 memcpy(pagebuffer
+ page_offset
,
2199 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
2209 /* By checking that offset is correct here, we also
2210 fix a clang warning */
2211 assert(offset
% pPrivate
->page_size
== 0);
2213 /* intermediate large pages */
2214 /* also - the final *terminal* */
2215 /* if that terminal page is a full page */
2216 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2217 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2219 while ((page_cur
< page_end
) &&
2220 (count
>= pPrivate
->page_size
)) {
2221 r
= sam4_page_write(pPrivate
, page_cur
, buffer
);
2224 count
-= pPrivate
->page_size
;
2225 buffer
+= pPrivate
->page_size
;
2229 /* terminal partial page? */
2231 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2232 /* we have a partial page */
2233 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
2236 /* data goes at start */
2237 memcpy(pagebuffer
, buffer
, count
);
2238 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
2250 COMMAND_HANDLER(sam4_handle_info_command
)
2252 struct sam4_chip
*pChip
;
2253 pChip
= get_current_sam4(CMD_CTX
);
2260 /* bank0 must exist before we can do anything */
2261 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2264 command_print(CMD_CTX
,
2265 "Please define bank %d via command: flash bank %s ... ",
2267 at91sam4_flash
.name
);
2271 /* if bank 0 is not probed, then probe it */
2272 if (!(pChip
->details
.bank
[0].probed
)) {
2273 r
= sam4_auto_probe(pChip
->details
.bank
[0].pBank
);
2277 /* above guarantees the "chip details" structure is valid */
2278 /* and thus, bank private areas are valid */
2279 /* and we have a SAM4 chip, what a concept! */
2281 /* auto-probe other banks, 0 done above */
2282 for (x
= 1; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
2283 /* skip banks not present */
2284 if (!(pChip
->details
.bank
[x
].present
))
2287 if (pChip
->details
.bank
[x
].pBank
== NULL
)
2290 if (pChip
->details
.bank
[x
].probed
)
2293 r
= sam4_auto_probe(pChip
->details
.bank
[x
].pBank
);
2298 r
= sam4_GetInfo(pChip
);
2299 if (r
!= ERROR_OK
) {
2300 LOG_DEBUG("Sam4Info, Failed %d", r
);
2307 COMMAND_HANDLER(sam4_handle_gpnvm_command
)
2311 struct sam4_chip
*pChip
;
2313 pChip
= get_current_sam4(CMD_CTX
);
2317 if (pChip
->target
->state
!= TARGET_HALTED
) {
2318 LOG_ERROR("sam4 - target not halted");
2319 return ERROR_TARGET_NOT_HALTED
;
2322 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2323 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
2324 at91sam4_flash
.name
);
2327 if (!pChip
->details
.bank
[0].probed
) {
2328 r
= sam4_auto_probe(pChip
->details
.bank
[0].pBank
);
2335 return ERROR_COMMAND_SYNTAX_ERROR
;
2344 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
2348 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
2354 if (0 == strcmp("show", CMD_ARGV
[0])) {
2358 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
2359 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
2362 command_print(CMD_CTX
, "sam4-gpnvm%u: %u", x
, v
);
2366 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
2367 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
2368 command_print(CMD_CTX
, "sam4-gpnvm%u: %u", who
, v
);
2371 command_print(CMD_CTX
, "sam4-gpnvm invalid GPNVM: %u", who
);
2372 return ERROR_COMMAND_SYNTAX_ERROR
;
2377 command_print(CMD_CTX
, "Missing GPNVM number");
2378 return ERROR_COMMAND_SYNTAX_ERROR
;
2381 if (0 == strcmp("set", CMD_ARGV
[0]))
2382 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
2383 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
2384 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
2385 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
2387 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
2388 r
= ERROR_COMMAND_SYNTAX_ERROR
;
2393 COMMAND_HANDLER(sam4_handle_slowclk_command
)
2395 struct sam4_chip
*pChip
;
2397 pChip
= get_current_sam4(CMD_CTX
);
2409 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
2411 /* absurd slow clock of 200Khz? */
2412 command_print(CMD_CTX
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
2413 return ERROR_COMMAND_SYNTAX_ERROR
;
2415 pChip
->cfg
.slow_freq
= v
;
2420 command_print(CMD_CTX
, "Too many parameters");
2421 return ERROR_COMMAND_SYNTAX_ERROR
;
2424 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
2425 (int)(pChip
->cfg
.slow_freq
/ 1000),
2426 (int)(pChip
->cfg
.slow_freq
% 1000));
2430 static const struct command_registration at91sam4_exec_command_handlers
[] = {
2433 .handler
= sam4_handle_gpnvm_command
,
2434 .mode
= COMMAND_EXEC
,
2435 .usage
= "[('clr'|'set'|'show') bitnum]",
2436 .help
= "Without arguments, shows all bits in the gpnvm "
2437 "register. Otherwise, clears, sets, or shows one "
2438 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2442 .handler
= sam4_handle_info_command
,
2443 .mode
= COMMAND_EXEC
,
2444 .help
= "Print information about the current at91sam4 chip"
2445 "and its flash configuration.",
2449 .handler
= sam4_handle_slowclk_command
,
2450 .mode
= COMMAND_EXEC
,
2451 .usage
= "[clock_hz]",
2452 .help
= "Display or set the slowclock frequency "
2453 "(default 32768 Hz).",
2455 COMMAND_REGISTRATION_DONE
2457 static const struct command_registration at91sam4_command_handlers
[] = {
2460 .mode
= COMMAND_ANY
,
2461 .help
= "at91sam4 flash command group",
2463 .chain
= at91sam4_exec_command_handlers
,
2465 COMMAND_REGISTRATION_DONE
2468 struct flash_driver at91sam4_flash
= {
2470 .commands
= at91sam4_command_handlers
,
2471 .flash_bank_command
= sam4_flash_bank_command
,
2472 .erase
= sam4_erase
,
2473 .protect
= sam4_protect
,
2474 .write
= sam4_write
,
2475 .read
= default_flash_read
,
2476 .probe
= sam4_probe
,
2477 .auto_probe
= sam4_auto_probe
,
2478 .erase_check
= default_flash_blank_check
,
2479 .protect_check
= sam4_protect_check
,
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