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Add remote bitbang write buffer.
[openocd.git] / src / flash / nor / at91sam4.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
24
25 /* Some of the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
27
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
33 *
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
38 *
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
41 *
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
44 *
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
56 */
57 /* END ATMEL COPYRIGHT */
58
59 #ifdef HAVE_CONFIG_H
60 #include "config.h"
61 #endif
62
63 #include "imp.h"
64 #include <helper/time_support.h>
65
66 #define REG_NAME_WIDTH (12)
67
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
71
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
78
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
82
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
100
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
105
106 extern const struct flash_driver at91sam4_flash;
107
108 static float _tomhz(uint32_t freq_hz)
109 {
110 float f;
111
112 f = ((float)(freq_hz)) / 1000000.0;
113 return f;
114 }
115
116 /* How the chip is configured. */
117 struct sam4_cfg {
118 uint32_t unique_id[4];
119
120 uint32_t slow_freq;
121 uint32_t rc_freq;
122 uint32_t mainosc_freq;
123 uint32_t plla_freq;
124 uint32_t mclk_freq;
125 uint32_t cpu_freq;
126 uint32_t fclk_freq;
127 uint32_t pclk0_freq;
128 uint32_t pclk1_freq;
129 uint32_t pclk2_freq;
130
131
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID;
136
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
139 uint32_t PMC_SCSR;
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
141 uint32_t PMC_PCSR;
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
143 uint32_t CKGR_UCKR;
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
145 uint32_t CKGR_MOR;
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
147 uint32_t CKGR_MCFR;
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
149 uint32_t CKGR_PLLAR;
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
151 uint32_t PMC_MCKR;
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
153 uint32_t PMC_PCK0;
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
155 uint32_t PMC_PCK1;
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
157 uint32_t PMC_PCK2;
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
159 uint32_t PMC_SR;
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
161 uint32_t PMC_IMR;
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
163 uint32_t PMC_FSMR;
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 uint32_t PMC_FSPR;
166 };
167
168 struct sam4_bank_private {
169 bool probed;
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
175
176 /* so we can find the chip we belong to */
177 struct sam4_chip *pChip;
178 /* so we can find the original bank pointer */
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
183 uint32_t flash_wait_states;
184 bool present;
185 unsigned size_bytes;
186 unsigned nsectors;
187 unsigned sector_size;
188 unsigned page_size;
189 };
190
191 struct sam4_chip_details {
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr;
200 const char *name;
201
202 unsigned n_gpnvms;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm[SAM4_N_NVM_BITS];
205 unsigned total_flash_size;
206 unsigned total_sram_size;
207 unsigned n_banks;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
211 };
212
213 struct sam4_chip {
214 struct sam4_chip *next;
215 bool probed;
216
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details;
219 struct target *target;
220 struct sam4_cfg cfg;
221 };
222
223
224 struct sam4_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam4_chip *pInfo);
227 };
228
229 static struct sam4_chip *all_sam4_chips;
230
231 static struct sam4_chip *get_current_sam4(struct command_invocation *cmd)
232 {
233 struct target *t;
234 static struct sam4_chip *p;
235
236 t = get_current_target(cmd->ctx);
237 if (!t) {
238 command_print(cmd, "No current target?");
239 return NULL;
240 }
241
242 p = all_sam4_chips;
243 if (!p) {
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd, "No SAM4 chips exist?");
247 return NULL;
248 }
249
250 while (p) {
251 if (p->target == t)
252 return p;
253 p = p->next;
254 }
255 command_print(cmd, "Cannot find SAM4 chip?");
256 return NULL;
257 }
258
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
263
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
268 {
269 .chipid_cidr = 0xA66D0EE0,
270 .name = "at91sam4c32e",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
273 .n_gpnvms = 3,
274 .n_banks = 2,
275 /* .bank[0] = { */
276 {
277 {
278 .probed = false,
279 .pChip = NULL,
280 .pBank = NULL,
281 .bank_number = 0,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
285 .present = true,
286 .size_bytes = 1024 * 1024,
287 .nsectors = 128,
288 .sector_size = 8192,
289 .page_size = 512,
290 },
291 /* .bank[1] = { */
292 {
293 .probed = false,
294 .pChip = NULL,
295 .pBank = NULL,
296 .bank_number = 1,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
300 .present = true,
301 .size_bytes = 1024 * 1024,
302 .nsectors = 128,
303 .sector_size = 8192,
304 .page_size = 512,
305 },
306 },
307 },
308 /* at91sam4c32c - LQFP100 */
309 {
310 .chipid_cidr = 0xA64D0EE0,
311 .name = "at91sam4c32c",
312 .total_flash_size = 2024 * 1024,
313 .total_sram_size = 256 * 1024,
314 .n_gpnvms = 3,
315 .n_banks = 2,
316 /* .bank[0] = { */
317 {
318 {
319 .probed = false,
320 .pChip = NULL,
321 .pBank = NULL,
322 .bank_number = 0,
323 .base_address = FLASH_BANK0_BASE_C32,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
326 .present = true,
327 .size_bytes = 1024 * 1024,
328 .nsectors = 128,
329 .sector_size = 8192,
330 .page_size = 512,
331 },
332 /* .bank[1] = { */
333 {
334 .probed = false,
335 .pChip = NULL,
336 .pBank = NULL,
337 .bank_number = 1,
338 .base_address = FLASH_BANK1_BASE_C32,
339 .controller_address = 0x400e0c00,
340 .flash_wait_states = 5,
341 .present = true,
342 .size_bytes = 1024 * 1024,
343 .nsectors = 128,
344 .sector_size = 8192,
345 .page_size = 512,
346 },
347 },
348 },
349 /* at91sam4c16c - LQFP100 */
350 {
351 .chipid_cidr = 0xA64C0CE0,
352 .name = "at91sam4c16c",
353 .total_flash_size = 1024 * 1024,
354 .total_sram_size = 128 * 1024,
355 .n_gpnvms = 2,
356 .n_banks = 1,
357 {
358 /* .bank[0] = {*/
359 {
360 .probed = false,
361 .pChip = NULL,
362 .pBank = NULL,
363 .bank_number = 0,
364 .base_address = FLASH_BANK_BASE_C,
365 .controller_address = 0x400e0a00,
366 .flash_wait_states = 5,
367 .present = true,
368 .size_bytes = 1024 * 1024,
369 .nsectors = 128,
370 .sector_size = 8192,
371 .page_size = 512,
372 },
373 /* .bank[1] = {*/
374 {
375 .present = false,
376 .probed = false,
377 .bank_number = 1,
378
379 },
380 },
381 },
382 /* at91sam4c8c - LQFP100 */
383 {
384 .chipid_cidr = 0xA64C0AE0,
385 .name = "at91sam4c8c",
386 .total_flash_size = 512 * 1024,
387 .total_sram_size = 128 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390 {
391 /* .bank[0] = {*/
392 {
393 .probed = false,
394 .pChip = NULL,
395 .pBank = NULL,
396 .bank_number = 0,
397 .base_address = FLASH_BANK_BASE_C,
398 .controller_address = 0x400e0a00,
399 .flash_wait_states = 5,
400 .present = true,
401 .size_bytes = 512 * 1024,
402 .nsectors = 64,
403 .sector_size = 8192,
404 .page_size = 512,
405 },
406 /* .bank[1] = {*/
407 {
408 .present = false,
409 .probed = false,
410 .bank_number = 1,
411
412 },
413 },
414 },
415 /* at91sam4c4c (rev B) - LQFP100 */
416 {
417 .chipid_cidr = 0xA64C0CE5,
418 .name = "at91sam4c4c",
419 .total_flash_size = 256 * 1024,
420 .total_sram_size = 128 * 1024,
421 .n_gpnvms = 2,
422 .n_banks = 1,
423 {
424 /* .bank[0] = {*/
425 {
426 .probed = false,
427 .pChip = NULL,
428 .pBank = NULL,
429 .bank_number = 0,
430 .base_address = FLASH_BANK_BASE_C,
431 .controller_address = 0x400e0a00,
432 .flash_wait_states = 5,
433 .present = true,
434 .size_bytes = 256 * 1024,
435 .nsectors = 32,
436 .sector_size = 8192,
437 .page_size = 512,
438 },
439 /* .bank[1] = {*/
440 {
441 .present = false,
442 .probed = false,
443 .bank_number = 1,
444
445 },
446 },
447 },
448
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
451 {
452 .chipid_cidr = 0xA3CC0CE0,
453 .name = "at91sam4e16e",
454 .total_flash_size = 1024 * 1024,
455 .total_sram_size = 128 * 1024,
456 .n_gpnvms = 2,
457 .n_banks = 1,
458 {
459 /* .bank[0] = {*/
460 {
461 .probed = false,
462 .pChip = NULL,
463 .pBank = NULL,
464 .bank_number = 0,
465 .base_address = FLASH_BANK_BASE_S,
466 .controller_address = 0x400e0a00,
467 .flash_wait_states = 5,
468 .present = true,
469 .size_bytes = 1024 * 1024,
470 .nsectors = 128,
471 .sector_size = 8192,
472 .page_size = 512,
473 },
474 /* .bank[1] = {*/
475 {
476 .present = false,
477 .probed = false,
478 .bank_number = 1,
479
480 },
481 },
482 },
483
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
486 {
487 .chipid_cidr = 0x293B0AE0,
488 .name = "at91sam4n8a",
489 .total_flash_size = 512 * 1024,
490 .total_sram_size = 64 * 1024,
491 .n_gpnvms = 2,
492 .n_banks = 1,
493 {
494 /* .bank[0] = {*/
495 {
496 .probed = false,
497 .pChip = NULL,
498 .pBank = NULL,
499 .bank_number = 0,
500 .base_address = FLASH_BANK_BASE_S,
501 .controller_address = 0x400e0a00,
502 .flash_wait_states = 5,
503 .present = true,
504 .size_bytes = 512 * 1024,
505 .nsectors = 64,
506 .sector_size = 8192,
507 .page_size = 512,
508 },
509 /* .bank[1] = {*/
510 {
511 .present = false,
512 .probed = false,
513 .bank_number = 1,
514
515 },
516 },
517 },
518 /*atsam4n8b - LQFP64/QFN64*/
519 {
520 .chipid_cidr = 0x294B0AE0,
521 .name = "at91sam4n8b",
522 .total_flash_size = 512 * 1024,
523 .total_sram_size = 64 * 1024,
524 .n_gpnvms = 2,
525 .n_banks = 1,
526 {
527 /* .bank[0] = {*/
528 {
529 .probed = false,
530 .pChip = NULL,
531 .pBank = NULL,
532 .bank_number = 0,
533 .base_address = FLASH_BANK_BASE_S,
534 .controller_address = 0x400e0a00,
535 .flash_wait_states = 5,
536 .present = true,
537 .size_bytes = 512 * 1024,
538 .nsectors = 64,
539 .sector_size = 8192,
540 .page_size = 512,
541 },
542 /* .bank[1] = {*/
543 {
544 .present = false,
545 .probed = false,
546 .bank_number = 1,
547
548 },
549 },
550 },
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
552 {
553 .chipid_cidr = 0x295B0AE0,
554 .name = "at91sam4n8c",
555 .total_flash_size = 512 * 1024,
556 .total_sram_size = 64 * 1024,
557 .n_gpnvms = 2,
558 .n_banks = 1,
559 {
560 /* .bank[0] = {*/
561 {
562 .probed = false,
563 .pChip = NULL,
564 .pBank = NULL,
565 .bank_number = 0,
566 .base_address = FLASH_BANK_BASE_S,
567 .controller_address = 0x400e0a00,
568 .flash_wait_states = 5,
569 .present = true,
570 .size_bytes = 512 * 1024,
571 .nsectors = 64,
572 .sector_size = 8192,
573 .page_size = 512,
574 },
575 /* .bank[1] = {*/
576 {
577 .present = false,
578 .probed = false,
579 .bank_number = 1,
580
581 },
582 },
583 },
584 /*atsam4n16b - LQFP64/QFN64*/
585 {
586 .chipid_cidr = 0x29460CE0,
587 .name = "at91sam4n16b",
588 .total_flash_size = 1024 * 1024,
589 .total_sram_size = 80 * 1024,
590 .n_gpnvms = 2,
591 .n_banks = 1,
592 {
593 /* .bank[0] = {*/
594 {
595 .probed = false,
596 .pChip = NULL,
597 .pBank = NULL,
598 .bank_number = 0,
599 .base_address = FLASH_BANK_BASE_S,
600 .controller_address = 0x400e0a00,
601 .flash_wait_states = 5,
602 .present = true,
603 .size_bytes = 1024 * 1024,
604 .nsectors = 128,
605 .sector_size = 8192,
606 .page_size = 512,
607 },
608 /* .bank[1] = {*/
609 {
610 .present = false,
611 .probed = false,
612 .bank_number = 1,
613
614 },
615 },
616 },
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
618 {
619 .chipid_cidr = 0x29560CE0,
620 .name = "at91sam4n16c",
621 .total_flash_size = 1024 * 1024,
622 .total_sram_size = 80 * 1024,
623 .n_gpnvms = 2,
624 .n_banks = 1,
625 {
626 /* .bank[0] = {*/
627 {
628 .probed = false,
629 .pChip = NULL,
630 .pBank = NULL,
631 .bank_number = 0,
632 .base_address = FLASH_BANK_BASE_S,
633 .controller_address = 0x400e0a00,
634 .flash_wait_states = 5,
635 .present = true,
636 .size_bytes = 1024 * 1024,
637 .nsectors = 128,
638 .sector_size = 8192,
639 .page_size = 512,
640 },
641 /* .bank[1] = {*/
642 {
643 .present = false,
644 .probed = false,
645 .bank_number = 1,
646
647 },
648 },
649 },
650
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
653 {
654 .chipid_cidr = 0x28AC0CE0,
655 .name = "at91sam4s16c",
656 .total_flash_size = 1024 * 1024,
657 .total_sram_size = 128 * 1024,
658 .n_gpnvms = 2,
659 .n_banks = 1,
660 {
661 /* .bank[0] = {*/
662 {
663 .probed = false,
664 .pChip = NULL,
665 .pBank = NULL,
666 .bank_number = 0,
667 .base_address = FLASH_BANK_BASE_S,
668 .controller_address = 0x400e0a00,
669 .flash_wait_states = 5,
670 .present = true,
671 .size_bytes = 1024 * 1024,
672 .nsectors = 128,
673 .sector_size = 8192,
674 .page_size = 512,
675 },
676 /* .bank[1] = {*/
677 {
678 .present = false,
679 .probed = false,
680 .bank_number = 1,
681
682 },
683 },
684 },
685 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
686 {
687 .chipid_cidr = 0x28a70ce0,
688 .name = "at91sam4sa16c",
689 .total_flash_size = 1024 * 1024,
690 .total_sram_size = 160 * 1024,
691 .n_gpnvms = 2,
692 .n_banks = 1,
693
694 /* .bank[0] = { */
695 {
696 {
697 .probed = false,
698 .pChip = NULL,
699 .pBank = NULL,
700 .bank_number = 0,
701 .base_address = FLASH_BANK_BASE_S,
702 .controller_address = 0x400e0a00,
703 .flash_wait_states = 5,
704 .present = true,
705 .size_bytes = 1024 * 1024,
706 .nsectors = 128,
707 .sector_size = 8192,
708 .page_size = 512,
709 },
710 /* .bank[1] = {*/
711 {
712 .present = false,
713 .probed = false,
714 .bank_number = 1,
715
716 },
717 },
718 },
719 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
720 {
721 .chipid_cidr = 0x289C0CE0,
722 .name = "at91sam4s16b",
723 .total_flash_size = 1024 * 1024,
724 .total_sram_size = 128 * 1024,
725 .n_gpnvms = 2,
726 .n_banks = 1,
727 {
728 /* .bank[0] = {*/
729 {
730 .probed = false,
731 .pChip = NULL,
732 .pBank = NULL,
733 .bank_number = 0,
734 .base_address = FLASH_BANK_BASE_S,
735 .controller_address = 0x400e0a00,
736 .flash_wait_states = 5,
737 .present = true,
738 .size_bytes = 1024 * 1024,
739 .nsectors = 128,
740 .sector_size = 8192,
741 .page_size = 512,
742 },
743 /* .bank[1] = {*/
744 {
745 .present = false,
746 .probed = false,
747 .bank_number = 1,
748
749 },
750 },
751 },
752 /*atsam4sa16b - LQFP64/QFN64*/
753 {
754 .chipid_cidr = 0x28970CE0,
755 .name = "at91sam4sa16b",
756 .total_flash_size = 1024 * 1024,
757 .total_sram_size = 160 * 1024,
758 .n_gpnvms = 2,
759 .n_banks = 1,
760 {
761 /* .bank[0] = {*/
762 {
763 .probed = false,
764 .pChip = NULL,
765 .pBank = NULL,
766 .bank_number = 0,
767 .base_address = FLASH_BANK_BASE_S,
768 .controller_address = 0x400e0a00,
769 .flash_wait_states = 5,
770 .present = true,
771 .size_bytes = 1024 * 1024,
772 .nsectors = 128,
773 .sector_size = 8192,
774 .page_size = 512,
775 },
776 /* .bank[1] = {*/
777 {
778 .present = false,
779 .probed = false,
780 .bank_number = 1,
781
782 },
783 },
784 },
785 /*atsam4s16a - LQFP48/QFN48*/
786 {
787 .chipid_cidr = 0x288C0CE0,
788 .name = "at91sam4s16a",
789 .total_flash_size = 1024 * 1024,
790 .total_sram_size = 128 * 1024,
791 .n_gpnvms = 2,
792 .n_banks = 1,
793 {
794 /* .bank[0] = {*/
795 {
796 .probed = false,
797 .pChip = NULL,
798 .pBank = NULL,
799 .bank_number = 0,
800 .base_address = FLASH_BANK_BASE_S,
801 .controller_address = 0x400e0a00,
802 .flash_wait_states = 5,
803 .present = true,
804 .size_bytes = 1024 * 1024,
805 .nsectors = 128,
806 .sector_size = 8192,
807 .page_size = 512,
808 },
809 /* .bank[1] = {*/
810 {
811 .present = false,
812 .probed = false,
813 .bank_number = 1,
814
815 },
816 },
817 },
818 /*atsam4s8c - LQFP100/BGA100*/
819 {
820 .chipid_cidr = 0x28AC0AE0,
821 .name = "at91sam4s8c",
822 .total_flash_size = 512 * 1024,
823 .total_sram_size = 128 * 1024,
824 .n_gpnvms = 2,
825 .n_banks = 1,
826 {
827 /* .bank[0] = {*/
828 {
829 .probed = false,
830 .pChip = NULL,
831 .pBank = NULL,
832 .bank_number = 0,
833 .base_address = FLASH_BANK_BASE_S,
834 .controller_address = 0x400e0a00,
835 .flash_wait_states = 5,
836 .present = true,
837 .size_bytes = 512 * 1024,
838 .nsectors = 64,
839 .sector_size = 8192,
840 .page_size = 512,
841 },
842 /* .bank[1] = {*/
843 {
844 .present = false,
845 .probed = false,
846 .bank_number = 1,
847
848 },
849 },
850 },
851 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
852 {
853 .chipid_cidr = 0x289C0AE0,
854 .name = "at91sam4s8b",
855 .total_flash_size = 512 * 1024,
856 .total_sram_size = 128 * 1024,
857 .n_gpnvms = 2,
858 .n_banks = 1,
859 {
860 /* .bank[0] = {*/
861 {
862 .probed = false,
863 .pChip = NULL,
864 .pBank = NULL,
865 .bank_number = 0,
866 .base_address = FLASH_BANK_BASE_S,
867 .controller_address = 0x400e0a00,
868 .flash_wait_states = 5,
869 .present = true,
870 .size_bytes = 512 * 1024,
871 .nsectors = 64,
872 .sector_size = 8192,
873 .page_size = 512,
874 },
875 /* .bank[1] = {*/
876 {
877 .present = false,
878 .probed = false,
879 .bank_number = 1,
880
881 },
882 },
883 },
884 /*atsam4s8a - LQFP48/BGA48*/
885 {
886 .chipid_cidr = 0x288C0AE0,
887 .name = "at91sam4s8a",
888 .total_flash_size = 512 * 1024,
889 .total_sram_size = 128 * 1024,
890 .n_gpnvms = 2,
891 .n_banks = 1,
892 {
893 /* .bank[0] = {*/
894 {
895 .probed = false,
896 .pChip = NULL,
897 .pBank = NULL,
898 .bank_number = 0,
899 .base_address = FLASH_BANK_BASE_S,
900 .controller_address = 0x400e0a00,
901 .flash_wait_states = 5,
902 .present = true,
903 .size_bytes = 512 * 1024,
904 .nsectors = 64,
905 .sector_size = 8192,
906 .page_size = 512,
907 },
908 /* .bank[1] = {*/
909 {
910 .present = false,
911 .probed = false,
912 .bank_number = 1,
913
914 },
915 },
916 },
917
918 /*atsam4s4c - LQFP100/BGA100*/
919 {
920 .chipid_cidr = 0x28ab09e0,
921 .name = "at91sam4s4c",
922 .total_flash_size = 256 * 1024,
923 .total_sram_size = 64 * 1024,
924 .n_gpnvms = 2,
925 .n_banks = 1,
926 {
927 /* .bank[0] = {*/
928 {
929 .probed = false,
930 .pChip = NULL,
931 .pBank = NULL,
932 .bank_number = 0,
933 .base_address = FLASH_BANK_BASE_S,
934 .controller_address = 0x400e0a00,
935 .flash_wait_states = 5,
936 .present = true,
937 .size_bytes = 256 * 1024,
938 .nsectors = 32,
939 .sector_size = 8192,
940 .page_size = 512,
941 },
942 /* .bank[1] = {*/
943 {
944 .present = false,
945 .probed = false,
946 .bank_number = 1,
947
948 },
949 },
950 },
951
952 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
953 {
954 .chipid_cidr = 0x289b09e0,
955 .name = "at91sam4s4b",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 64 * 1024,
958 .n_gpnvms = 2,
959 .n_banks = 1,
960 {
961 /* .bank[0] = {*/
962 {
963 .probed = false,
964 .pChip = NULL,
965 .pBank = NULL,
966 .bank_number = 0,
967 .base_address = FLASH_BANK_BASE_S,
968 .controller_address = 0x400e0a00,
969 .flash_wait_states = 5,
970 .present = true,
971 .size_bytes = 256 * 1024,
972 .nsectors = 32,
973 .sector_size = 8192,
974 .page_size = 512,
975 },
976 /* .bank[1] = {*/
977 {
978 .present = false,
979 .probed = false,
980 .bank_number = 1,
981
982 },
983 },
984 },
985
986 /*atsam4s4a - LQFP48/QFN48*/
987 {
988 .chipid_cidr = 0x288b09e0,
989 .name = "at91sam4s4a",
990 .total_flash_size = 256 * 1024,
991 .total_sram_size = 64 * 1024,
992 .n_gpnvms = 2,
993 .n_banks = 1,
994 {
995 /* .bank[0] = {*/
996 {
997 .probed = false,
998 .pChip = NULL,
999 .pBank = NULL,
1000 .bank_number = 0,
1001 .base_address = FLASH_BANK_BASE_S,
1002 .controller_address = 0x400e0a00,
1003 .flash_wait_states = 5,
1004 .present = true,
1005 .size_bytes = 256 * 1024,
1006 .nsectors = 32,
1007 .sector_size = 8192,
1008 .page_size = 512,
1009 },
1010 /* .bank[1] = {*/
1011 {
1012 .present = false,
1013 .probed = false,
1014 .bank_number = 1,
1015
1016 },
1017 },
1018 },
1019
1020 /*atsam4s2c - LQFP100/BGA100*/
1021 {
1022 .chipid_cidr = 0x28ab07e0,
1023 .name = "at91sam4s2c",
1024 .total_flash_size = 128 * 1024,
1025 .total_sram_size = 64 * 1024,
1026 .n_gpnvms = 2,
1027 .n_banks = 1,
1028 {
1029 /* .bank[0] = {*/
1030 {
1031 .probed = false,
1032 .pChip = NULL,
1033 .pBank = NULL,
1034 .bank_number = 0,
1035 .base_address = FLASH_BANK_BASE_S,
1036 .controller_address = 0x400e0a00,
1037 .flash_wait_states = 5,
1038 .present = true,
1039 .size_bytes = 128 * 1024,
1040 .nsectors = 16,
1041 .sector_size = 8192,
1042 .page_size = 512,
1043 },
1044 /* .bank[1] = {*/
1045 {
1046 .present = false,
1047 .probed = false,
1048 .bank_number = 1,
1049
1050 },
1051 },
1052 },
1053
1054 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1055 {
1056 .chipid_cidr = 0x289b07e0,
1057 .name = "at91sam4s2b",
1058 .total_flash_size = 128 * 1024,
1059 .total_sram_size = 64 * 1024,
1060 .n_gpnvms = 2,
1061 .n_banks = 1,
1062 {
1063 /* .bank[0] = {*/
1064 {
1065 .probed = false,
1066 .pChip = NULL,
1067 .pBank = NULL,
1068 .bank_number = 0,
1069 .base_address = FLASH_BANK_BASE_S,
1070 .controller_address = 0x400e0a00,
1071 .flash_wait_states = 5,
1072 .present = true,
1073 .size_bytes = 128 * 1024,
1074 .nsectors = 16,
1075 .sector_size = 8192,
1076 .page_size = 512,
1077 },
1078 /* .bank[1] = {*/
1079 {
1080 .present = false,
1081 .probed = false,
1082 .bank_number = 1,
1083
1084 },
1085 },
1086 },
1087
1088 /*atsam4s2a - LQFP48/QFN48*/
1089 {
1090 .chipid_cidr = 0x288b07e0,
1091 .name = "at91sam4s2a",
1092 .total_flash_size = 128 * 1024,
1093 .total_sram_size = 64 * 1024,
1094 .n_gpnvms = 2,
1095 .n_banks = 1,
1096 {
1097 /* .bank[0] = {*/
1098 {
1099 .probed = false,
1100 .pChip = NULL,
1101 .pBank = NULL,
1102 .bank_number = 0,
1103 .base_address = FLASH_BANK_BASE_S,
1104 .controller_address = 0x400e0a00,
1105 .flash_wait_states = 5,
1106 .present = true,
1107 .size_bytes = 128 * 1024,
1108 .nsectors = 16,
1109 .sector_size = 8192,
1110 .page_size = 512,
1111 },
1112 /* .bank[1] = {*/
1113 {
1114 .present = false,
1115 .probed = false,
1116 .bank_number = 1,
1117
1118 },
1119 },
1120 },
1121
1122 /*at91sam4sd32c - LQFP100/BGA100*/
1123 {
1124 .chipid_cidr = 0x29a70ee0,
1125 .name = "at91sam4sd32c",
1126 .total_flash_size = 2048 * 1024,
1127 .total_sram_size = 160 * 1024,
1128 .n_gpnvms = 3,
1129 .n_banks = 2,
1130
1131 /* .bank[0] = { */
1132 {
1133 {
1134 .probed = false,
1135 .pChip = NULL,
1136 .pBank = NULL,
1137 .bank_number = 0,
1138 .base_address = FLASH_BANK0_BASE_SD,
1139 .controller_address = 0x400e0a00,
1140 .flash_wait_states = 5,
1141 .present = true,
1142 .size_bytes = 1024 * 1024,
1143 .nsectors = 128,
1144 .sector_size = 8192,
1145 .page_size = 512,
1146 },
1147
1148 /* .bank[1] = { */
1149 {
1150 .probed = false,
1151 .pChip = NULL,
1152 .pBank = NULL,
1153 .bank_number = 1,
1154 .base_address = FLASH_BANK1_BASE_2048K_SD,
1155 .controller_address = 0x400e0c00,
1156 .flash_wait_states = 5,
1157 .present = true,
1158 .size_bytes = 1024 * 1024,
1159 .nsectors = 128,
1160 .sector_size = 8192,
1161 .page_size = 512,
1162 },
1163 },
1164 },
1165
1166 /*at91sam4sd32b - LQFP64/BGA64*/
1167 {
1168 .chipid_cidr = 0x29970ee0,
1169 .name = "at91sam4sd32b",
1170 .total_flash_size = 2048 * 1024,
1171 .total_sram_size = 160 * 1024,
1172 .n_gpnvms = 3,
1173 .n_banks = 2,
1174
1175 /* .bank[0] = { */
1176 {
1177 {
1178 .probed = false,
1179 .pChip = NULL,
1180 .pBank = NULL,
1181 .bank_number = 0,
1182 .base_address = FLASH_BANK0_BASE_SD,
1183 .controller_address = 0x400e0a00,
1184 .flash_wait_states = 5,
1185 .present = true,
1186 .size_bytes = 1024 * 1024,
1187 .nsectors = 128,
1188 .sector_size = 8192,
1189 .page_size = 512,
1190 },
1191
1192 /* .bank[1] = { */
1193 {
1194 .probed = false,
1195 .pChip = NULL,
1196 .pBank = NULL,
1197 .bank_number = 1,
1198 .base_address = FLASH_BANK1_BASE_2048K_SD,
1199 .controller_address = 0x400e0c00,
1200 .flash_wait_states = 5,
1201 .present = true,
1202 .size_bytes = 1024 * 1024,
1203 .nsectors = 128,
1204 .sector_size = 8192,
1205 .page_size = 512,
1206 },
1207 },
1208 },
1209
1210 /*at91sam4sd16c - LQFP100/BGA100*/
1211 {
1212 .chipid_cidr = 0x29a70ce0,
1213 .name = "at91sam4sd16c",
1214 .total_flash_size = 1024 * 1024,
1215 .total_sram_size = 160 * 1024,
1216 .n_gpnvms = 3,
1217 .n_banks = 2,
1218
1219 /* .bank[0] = { */
1220 {
1221 {
1222 .probed = false,
1223 .pChip = NULL,
1224 .pBank = NULL,
1225 .bank_number = 0,
1226 .base_address = FLASH_BANK0_BASE_SD,
1227 .controller_address = 0x400e0a00,
1228 .flash_wait_states = 5,
1229 .present = true,
1230 .size_bytes = 512 * 1024,
1231 .nsectors = 64,
1232 .sector_size = 8192,
1233 .page_size = 512,
1234 },
1235
1236 /* .bank[1] = { */
1237 {
1238 .probed = false,
1239 .pChip = NULL,
1240 .pBank = NULL,
1241 .bank_number = 1,
1242 .base_address = FLASH_BANK1_BASE_1024K_SD,
1243 .controller_address = 0x400e0c00,
1244 .flash_wait_states = 5,
1245 .present = true,
1246 .size_bytes = 512 * 1024,
1247 .nsectors = 64,
1248 .sector_size = 8192,
1249 .page_size = 512,
1250 },
1251 },
1252 },
1253
1254 /*at91sam4sd16b - LQFP64/BGA64*/
1255 {
1256 .chipid_cidr = 0x29970ce0,
1257 .name = "at91sam4sd16b",
1258 .total_flash_size = 1024 * 1024,
1259 .total_sram_size = 160 * 1024,
1260 .n_gpnvms = 3,
1261 .n_banks = 2,
1262
1263 /* .bank[0] = { */
1264 {
1265 {
1266 .probed = false,
1267 .pChip = NULL,
1268 .pBank = NULL,
1269 .bank_number = 0,
1270 .base_address = FLASH_BANK0_BASE_SD,
1271 .controller_address = 0x400e0a00,
1272 .flash_wait_states = 5,
1273 .present = true,
1274 .size_bytes = 512 * 1024,
1275 .nsectors = 64,
1276 .sector_size = 8192,
1277 .page_size = 512,
1278 },
1279
1280 /* .bank[1] = { */
1281 {
1282 .probed = false,
1283 .pChip = NULL,
1284 .pBank = NULL,
1285 .bank_number = 1,
1286 .base_address = FLASH_BANK1_BASE_1024K_SD,
1287 .controller_address = 0x400e0c00,
1288 .flash_wait_states = 5,
1289 .present = true,
1290 .size_bytes = 512 * 1024,
1291 .nsectors = 64,
1292 .sector_size = 8192,
1293 .page_size = 512,
1294 },
1295 },
1296 },
1297
1298 /* atsamg53n19 */
1299 {
1300 .chipid_cidr = 0x247e0ae0,
1301 .name = "atsamg53n19",
1302 .total_flash_size = 512 * 1024,
1303 .total_sram_size = 96 * 1024,
1304 .n_gpnvms = 2,
1305 .n_banks = 1,
1306
1307 /* .bank[0] = {*/
1308 {
1309 {
1310 .probed = false,
1311 .pChip = NULL,
1312 .pBank = NULL,
1313 .bank_number = 0,
1314 .base_address = FLASH_BANK_BASE_S,
1315 .controller_address = 0x400e0a00,
1316 .flash_wait_states = 5,
1317 .present = true,
1318 .size_bytes = 512 * 1024,
1319 .nsectors = 64,
1320 .sector_size = 8192,
1321 .page_size = 512,
1322 },
1323 /* .bank[1] = {*/
1324 {
1325 .present = false,
1326 .probed = false,
1327 .bank_number = 1,
1328
1329 },
1330 }
1331 },
1332
1333 /* atsamg55g19 Rev.A */
1334 {
1335 .chipid_cidr = 0x24470ae0,
1336 .name = "atsamg55g19",
1337 .total_flash_size = 512 * 1024,
1338 .total_sram_size = 160 * 1024,
1339 .n_gpnvms = 2,
1340 .n_banks = 1,
1341
1342 {
1343 /* .bank[0] = */
1344 {
1345 .probed = false,
1346 .pChip = NULL,
1347 .pBank = NULL,
1348 .bank_number = 0,
1349 .base_address = FLASH_BANK_BASE_S,
1350 .controller_address = 0x400e0a00,
1351 .flash_wait_states = 5,
1352 .present = true,
1353 .size_bytes = 512 * 1024,
1354 .nsectors = 64,
1355 .sector_size = 8192,
1356 .page_size = 512,
1357 },
1358 /* .bank[1] = */
1359 {
1360 .present = false,
1361 .probed = false,
1362 .bank_number = 1,
1363 },
1364 }
1365 },
1366
1367 /* atsamg55g19 Rev.B */
1368 {
1369 .chipid_cidr = 0x24470ae1,
1370 .name = "atsamg55g19b",
1371 .total_flash_size = 512 * 1024,
1372 .total_sram_size = 160 * 1024,
1373 .n_gpnvms = 2,
1374 .n_banks = 1,
1375
1376 {
1377 /* .bank[0] = */
1378 {
1379 .probed = false,
1380 .pChip = NULL,
1381 .pBank = NULL,
1382 .bank_number = 0,
1383 .base_address = FLASH_BANK_BASE_S,
1384 .controller_address = 0x400e0a00,
1385 .flash_wait_states = 5,
1386 .present = true,
1387 .size_bytes = 512 * 1024,
1388 .nsectors = 64,
1389 .sector_size = 8192,
1390 .page_size = 512,
1391 },
1392 /* .bank[1] = */
1393 {
1394 .present = false,
1395 .probed = false,
1396 .bank_number = 1,
1397 },
1398 }
1399 },
1400
1401 /* atsamg55j19 Rev.A */
1402 {
1403 .chipid_cidr = 0x24570ae0,
1404 .name = "atsamg55j19",
1405 .total_flash_size = 512 * 1024,
1406 .total_sram_size = 160 * 1024,
1407 .n_gpnvms = 2,
1408 .n_banks = 1,
1409
1410 {
1411 /* .bank[0] = */
1412 {
1413 .probed = false,
1414 .pChip = NULL,
1415 .pBank = NULL,
1416 .bank_number = 0,
1417 .base_address = FLASH_BANK_BASE_S,
1418 .controller_address = 0x400e0a00,
1419 .flash_wait_states = 5,
1420 .present = true,
1421 .size_bytes = 512 * 1024,
1422 .nsectors = 64,
1423 .sector_size = 8192,
1424 .page_size = 512,
1425 },
1426 /* .bank[1] = */
1427 {
1428 .present = false,
1429 .probed = false,
1430 .bank_number = 1,
1431 },
1432 }
1433 },
1434
1435 /* atsamg55j19 Rev.B */
1436 {
1437 .chipid_cidr = 0x24570ae1,
1438 .name = "atsamg55j19b",
1439 .total_flash_size = 512 * 1024,
1440 .total_sram_size = 160 * 1024,
1441 .n_gpnvms = 2,
1442 .n_banks = 1,
1443
1444 {
1445 /* .bank[0] = */
1446 {
1447 .probed = false,
1448 .pChip = NULL,
1449 .pBank = NULL,
1450 .bank_number = 0,
1451 .base_address = FLASH_BANK_BASE_S,
1452 .controller_address = 0x400e0a00,
1453 .flash_wait_states = 5,
1454 .present = true,
1455 .size_bytes = 512 * 1024,
1456 .nsectors = 64,
1457 .sector_size = 8192,
1458 .page_size = 512,
1459 },
1460 /* .bank[1] = */
1461 {
1462 .present = false,
1463 .probed = false,
1464 .bank_number = 1,
1465 },
1466 }
1467 },
1468
1469 /* terminate */
1470 {
1471 .chipid_cidr = 0,
1472 .name = NULL,
1473 }
1474 };
1475
1476 /* Globals above */
1477 /***********************************************************************
1478 **********************************************************************
1479 **********************************************************************
1480 **********************************************************************
1481 **********************************************************************
1482 **********************************************************************/
1483 /* *ATMEL* style code - from the SAM4 driver code */
1484
1485 /**
1486 * Get the current status of the EEFC and
1487 * the value of some status bits (LOCKE, PROGE).
1488 * @param pPrivate - info about the bank
1489 * @param v - result goes here
1490 */
1491 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
1492 {
1493 int r;
1494 r = target_read_u32(pPrivate->pChip->target,
1495 pPrivate->controller_address + offset_EFC_FSR,
1496 v);
1497 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1498 (unsigned int)(*v),
1499 ((unsigned int)((*v >> 2) & 1)),
1500 ((unsigned int)((*v >> 1) & 1)),
1501 ((unsigned int)((*v >> 0) & 1)));
1502
1503 return r;
1504 }
1505
1506 /**
1507 * Get the result of the last executed command.
1508 * @param pPrivate - info about the bank
1509 * @param v - result goes here
1510 */
1511 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
1512 {
1513 int r;
1514 uint32_t rv;
1515 r = target_read_u32(pPrivate->pChip->target,
1516 pPrivate->controller_address + offset_EFC_FRR,
1517 &rv);
1518 if (v)
1519 *v = rv;
1520 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1521 return r;
1522 }
1523
1524 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
1525 unsigned command, unsigned argument)
1526 {
1527 uint32_t n, v;
1528 int r;
1529 int retry;
1530
1531 retry = 0;
1532 do_retry:
1533
1534 /* Check command & argument */
1535 switch (command) {
1536
1537 case AT91C_EFC_FCMD_WP:
1538 case AT91C_EFC_FCMD_WPL:
1539 case AT91C_EFC_FCMD_EWP:
1540 case AT91C_EFC_FCMD_EWPL:
1541 /* case AT91C_EFC_FCMD_EPL: */
1542 case AT91C_EFC_FCMD_EPA:
1543 case AT91C_EFC_FCMD_SLB:
1544 case AT91C_EFC_FCMD_CLB:
1545 n = (pPrivate->size_bytes / pPrivate->page_size);
1546 if (argument >= n)
1547 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1548 break;
1549
1550 case AT91C_EFC_FCMD_SFB:
1551 case AT91C_EFC_FCMD_CFB:
1552 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1553 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1554 pPrivate->pChip->details.n_gpnvms);
1555 }
1556 break;
1557
1558 case AT91C_EFC_FCMD_GETD:
1559 case AT91C_EFC_FCMD_EA:
1560 case AT91C_EFC_FCMD_GLB:
1561 case AT91C_EFC_FCMD_GFB:
1562 case AT91C_EFC_FCMD_STUI:
1563 case AT91C_EFC_FCMD_SPUI:
1564 if (argument != 0)
1565 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1566 break;
1567 default:
1568 LOG_ERROR("Unknown command %d", command);
1569 break;
1570 }
1571
1572 if (command == AT91C_EFC_FCMD_SPUI) {
1573 /* this is a very special situation. */
1574 /* Situation (1) - error/retry - see below */
1575 /* And we are being called recursively */
1576 /* Situation (2) - normal, finished reading unique id */
1577 } else {
1578 /* it should be "ready" */
1579 EFC_GetStatus(pPrivate, &v);
1580 if (v & 1) {
1581 /* then it is ready */
1582 /* we go on */
1583 } else {
1584 if (retry) {
1585 /* we have done this before */
1586 /* the controller is not responding. */
1587 LOG_ERROR("flash controller(%d) is not ready! Error",
1588 pPrivate->bank_number);
1589 return ERROR_FAIL;
1590 } else {
1591 retry++;
1592 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1593 pPrivate->bank_number);
1594 /* we do that by issuing the *STOP* command */
1595 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1596 /* above is recursive, and further recursion is blocked by */
1597 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1598 goto do_retry;
1599 }
1600 }
1601 }
1602
1603 v = (0x5A << 24) | (argument << 8) | command;
1604 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1605 r = target_write_u32(pPrivate->pBank->target,
1606 pPrivate->controller_address + offset_EFC_FCR, v);
1607 if (r != ERROR_OK)
1608 LOG_DEBUG("Error Write failed");
1609 return r;
1610 }
1611
1612 /**
1613 * Performs the given command and wait until its completion (or an error).
1614 * @param pPrivate - info about the bank
1615 * @param command - Command to perform.
1616 * @param argument - Optional command argument.
1617 * @param status - put command status bits here
1618 */
1619 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1620 unsigned command,
1621 unsigned argument,
1622 uint32_t *status)
1623 {
1624
1625 int r;
1626 uint32_t v;
1627 int64_t ms_now, ms_end;
1628
1629 /* default */
1630 if (status)
1631 *status = 0;
1632
1633 r = EFC_StartCommand(pPrivate, command, argument);
1634 if (r != ERROR_OK)
1635 return r;
1636
1637 ms_end = 10000 + timeval_ms();
1638
1639 do {
1640 r = EFC_GetStatus(pPrivate, &v);
1641 if (r != ERROR_OK)
1642 return r;
1643 ms_now = timeval_ms();
1644 if (ms_now > ms_end) {
1645 /* error */
1646 LOG_ERROR("Command timeout");
1647 return ERROR_FAIL;
1648 }
1649 } while ((v & 1) == 0);
1650
1651 /* error bits.. */
1652 if (status)
1653 *status = (v & 0x6);
1654 return ERROR_OK;
1655
1656 }
1657
1658 /**
1659 * Read the unique ID.
1660 * @param pPrivate - info about the bank
1661 * The unique ID is stored in the 'pPrivate' structure.
1662 */
1663 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1664 {
1665 int r;
1666 uint32_t v;
1667 int x;
1668 /* assume 0 */
1669 pPrivate->pChip->cfg.unique_id[0] = 0;
1670 pPrivate->pChip->cfg.unique_id[1] = 0;
1671 pPrivate->pChip->cfg.unique_id[2] = 0;
1672 pPrivate->pChip->cfg.unique_id[3] = 0;
1673
1674 LOG_DEBUG("Begin");
1675 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1676 if (r < 0)
1677 return r;
1678
1679 for (x = 0; x < 4; x++) {
1680 r = target_read_u32(pPrivate->pChip->target,
1681 pPrivate->pBank->base + (x * 4),
1682 &v);
1683 if (r < 0)
1684 return r;
1685 pPrivate->pChip->cfg.unique_id[x] = v;
1686 }
1687
1688 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1689 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1690 r,
1691 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1692 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1693 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1694 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1695 return r;
1696
1697 }
1698
1699 /**
1700 * Erases the entire flash.
1701 * @param pPrivate - the info about the bank.
1702 */
1703 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1704 {
1705 LOG_DEBUG("Here");
1706 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1707 }
1708
1709 /**
1710 * Erases the entire flash.
1711 * @param pPrivate - the info about the bank.
1712 * @param firstPage
1713 * @param numPages
1714 * @param status
1715 */
1716 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1717 int firstPage,
1718 int numPages,
1719 uint32_t *status)
1720 {
1721 LOG_DEBUG("Here");
1722 uint8_t erasePages;
1723 switch (numPages) {
1724 case 4:
1725 erasePages = 0x00;
1726 break;
1727 case 8:
1728 erasePages = 0x01;
1729 break;
1730 case 16:
1731 erasePages = 0x02;
1732 break;
1733 case 32:
1734 erasePages = 0x03;
1735 break;
1736 default:
1737 erasePages = 0x00;
1738 break;
1739 }
1740
1741 /* AT91C_EFC_FCMD_EPA
1742 * According to the datasheet FARG[15:2] defines the page from which
1743 * the erase will start.This page must be modulo 4, 8, 16 or 32
1744 * according to the number of pages to erase. FARG[1:0] defines the
1745 * number of pages to be erased. Previously (firstpage << 2) was used
1746 * to conform to this, seems it should not be shifted...
1747 */
1748 return EFC_PerformCommand(pPrivate,
1749 /* send Erase Page */
1750 AT91C_EFC_FCMD_EPA,
1751 (firstPage) | erasePages,
1752 status);
1753 }
1754
1755 /**
1756 * Gets current GPNVM state.
1757 * @param pPrivate - info about the bank.
1758 * @param gpnvm - GPNVM bit index.
1759 * @param puthere - result stored here.
1760 */
1761 /* ------------------------------------------------------------------------------ */
1762 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1763 {
1764 uint32_t v;
1765 int r;
1766
1767 LOG_DEBUG("Here");
1768 if (pPrivate->bank_number != 0) {
1769 LOG_ERROR("GPNVM only works with Bank0");
1770 return ERROR_FAIL;
1771 }
1772
1773 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1774 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1775 gpnvm, pPrivate->pChip->details.n_gpnvms);
1776 return ERROR_FAIL;
1777 }
1778
1779 /* Get GPNVMs status */
1780 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1781 if (r != ERROR_OK) {
1782 LOG_ERROR("Failed");
1783 return r;
1784 }
1785
1786 r = EFC_GetResult(pPrivate, &v);
1787
1788 if (puthere) {
1789 /* Check if GPNVM is set */
1790 /* get the bit and make it a 0/1 */
1791 *puthere = (v >> gpnvm) & 1;
1792 }
1793
1794 return r;
1795 }
1796
1797 /**
1798 * Clears the selected GPNVM bit.
1799 * @param pPrivate info about the bank
1800 * @param gpnvm GPNVM index.
1801 * @returns 0 if successful; otherwise returns an error code.
1802 */
1803 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1804 {
1805 int r;
1806 unsigned v;
1807
1808 LOG_DEBUG("Here");
1809 if (pPrivate->bank_number != 0) {
1810 LOG_ERROR("GPNVM only works with Bank0");
1811 return ERROR_FAIL;
1812 }
1813
1814 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1815 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1816 gpnvm, pPrivate->pChip->details.n_gpnvms);
1817 return ERROR_FAIL;
1818 }
1819
1820 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1821 if (r != ERROR_OK) {
1822 LOG_DEBUG("Failed: %d", r);
1823 return r;
1824 }
1825 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1826 LOG_DEBUG("End: %d", r);
1827 return r;
1828 }
1829
1830 /**
1831 * Sets the selected GPNVM bit.
1832 * @param pPrivate info about the bank
1833 * @param gpnvm GPNVM index.
1834 */
1835 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1836 {
1837 int r;
1838 unsigned v;
1839
1840 if (pPrivate->bank_number != 0) {
1841 LOG_ERROR("GPNVM only works with Bank0");
1842 return ERROR_FAIL;
1843 }
1844
1845 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1846 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1847 gpnvm, pPrivate->pChip->details.n_gpnvms);
1848 return ERROR_FAIL;
1849 }
1850
1851 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1852 if (r != ERROR_OK)
1853 return r;
1854 if (v) {
1855 /* already set */
1856 r = ERROR_OK;
1857 } else {
1858 /* set it */
1859 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1860 }
1861 return r;
1862 }
1863
1864 /**
1865 * Returns a bit field (at most 64) of locked regions within a page.
1866 * @param pPrivate info about the bank
1867 * @param v where to store locked bits
1868 */
1869 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1870 {
1871 int r;
1872 LOG_DEBUG("Here");
1873 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1874 if (r == ERROR_OK) {
1875 EFC_GetResult(pPrivate, v);
1876 EFC_GetResult(pPrivate, v);
1877 EFC_GetResult(pPrivate, v);
1878 r = EFC_GetResult(pPrivate, v);
1879 }
1880 LOG_DEBUG("End: %d", r);
1881 return r;
1882 }
1883
1884 /**
1885 * Unlocks all the regions in the given address range.
1886 * @param pPrivate info about the bank
1887 * @param start_sector first sector to unlock
1888 * @param end_sector last (inclusive) to unlock
1889 */
1890
1891 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1892 unsigned start_sector,
1893 unsigned end_sector)
1894 {
1895 int r;
1896 uint32_t status;
1897 uint32_t pg;
1898 uint32_t pages_per_sector;
1899
1900 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1901
1902 /* Unlock all pages */
1903 while (start_sector <= end_sector) {
1904 pg = start_sector * pages_per_sector;
1905
1906 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1907 if (r != ERROR_OK)
1908 return r;
1909 start_sector++;
1910 }
1911
1912 return ERROR_OK;
1913 }
1914
1915 /**
1916 * Locks regions
1917 * @param pPrivate - info about the bank
1918 * @param start_sector - first sector to lock
1919 * @param end_sector - last sector (inclusive) to lock
1920 */
1921 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1922 unsigned start_sector,
1923 unsigned end_sector)
1924 {
1925 uint32_t status;
1926 uint32_t pg;
1927 uint32_t pages_per_sector;
1928 int r;
1929
1930 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1931
1932 /* Lock all pages */
1933 while (start_sector <= end_sector) {
1934 pg = start_sector * pages_per_sector;
1935
1936 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1937 if (r != ERROR_OK)
1938 return r;
1939 start_sector++;
1940 }
1941 return ERROR_OK;
1942 }
1943
1944 /****** END SAM4 CODE ********/
1945
1946 /* begin helpful debug code */
1947 /* print the fieldname, the field value, in dec & hex, and return field value */
1948 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1949 const char *regname,
1950 uint32_t value,
1951 unsigned shift,
1952 unsigned width)
1953 {
1954 uint32_t v;
1955 int hwidth, dwidth;
1956
1957
1958 /* extract the field */
1959 v = value >> shift;
1960 v = v & ((1 << width)-1);
1961 if (width <= 16) {
1962 hwidth = 4;
1963 dwidth = 5;
1964 } else {
1965 hwidth = 8;
1966 dwidth = 12;
1967 }
1968
1969 /* show the basics */
1970 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
1971 REG_NAME_WIDTH, regname,
1972 dwidth, v,
1973 hwidth, v);
1974 return v;
1975 }
1976
1977 static const char _unknown[] = "unknown";
1978 static const char *const eproc_names[] = {
1979 "Cortex-M7", /* 0 */
1980 "arm946es", /* 1 */
1981 "arm7tdmi", /* 2 */
1982 "Cortex-M3", /* 3 */
1983 "arm920t", /* 4 */
1984 "arm926ejs", /* 5 */
1985 "Cortex-A5", /* 6 */
1986 "Cortex-M4", /* 7 */
1987 _unknown, /* 8 */
1988 _unknown, /* 9 */
1989 _unknown, /* 10 */
1990 _unknown, /* 11 */
1991 _unknown, /* 12 */
1992 _unknown, /* 13 */
1993 _unknown, /* 14 */
1994 _unknown, /* 15 */
1995 };
1996
1997 #define nvpsize2 nvpsize /* these two tables are identical */
1998 static const char *const nvpsize[] = {
1999 "none", /* 0 */
2000 "8K bytes", /* 1 */
2001 "16K bytes", /* 2 */
2002 "32K bytes", /* 3 */
2003 _unknown, /* 4 */
2004 "64K bytes", /* 5 */
2005 _unknown, /* 6 */
2006 "128K bytes", /* 7 */
2007 "160K bytes", /* 8 */
2008 "256K bytes", /* 9 */
2009 "512K bytes", /* 10 */
2010 _unknown, /* 11 */
2011 "1024K bytes", /* 12 */
2012 _unknown, /* 13 */
2013 "2048K bytes", /* 14 */
2014 _unknown, /* 15 */
2015 };
2016
2017 static const char *const sramsize[] = {
2018 "48K Bytes", /* 0 */
2019 "1K Bytes", /* 1 */
2020 "2K Bytes", /* 2 */
2021 "6K Bytes", /* 3 */
2022 "112K Bytes", /* 4 */
2023 "4K Bytes", /* 5 */
2024 "80K Bytes", /* 6 */
2025 "160K Bytes", /* 7 */
2026 "8K Bytes", /* 8 */
2027 "16K Bytes", /* 9 */
2028 "32K Bytes", /* 10 */
2029 "64K Bytes", /* 11 */
2030 "128K Bytes", /* 12 */
2031 "256K Bytes", /* 13 */
2032 "96K Bytes", /* 14 */
2033 "512K Bytes", /* 15 */
2034
2035 };
2036
2037 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2038 { 0x19, "AT91SAM9xx Series" },
2039 { 0x29, "AT91SAM9XExx Series" },
2040 { 0x34, "AT91x34 Series" },
2041 { 0x37, "CAP7 Series" },
2042 { 0x39, "CAP9 Series" },
2043 { 0x3B, "CAP11 Series" },
2044 { 0x3C, "ATSAM4E" },
2045 { 0x40, "AT91x40 Series" },
2046 { 0x42, "AT91x42 Series" },
2047 { 0x43, "SAMG51 Series"
2048 },
2049 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2050 { 0x45, "SAMG55 Series (64-pin)" },
2051 { 0x47, "SAMG53 Series"
2052 },
2053 { 0x55, "AT91x55 Series" },
2054 { 0x60, "AT91SAM7Axx Series" },
2055 { 0x61, "AT91SAM7AQxx Series" },
2056 { 0x63, "AT91x63 Series" },
2057 { 0x64, "SAM4CxxC (100-pin version)" },
2058 { 0x66, "SAM4CxxE (144-pin version)" },
2059 { 0x70, "AT91SAM7Sxx Series" },
2060 { 0x71, "AT91SAM7XCxx Series" },
2061 { 0x72, "AT91SAM7SExx Series" },
2062 { 0x73, "AT91SAM7Lxx Series" },
2063 { 0x75, "AT91SAM7Xxx Series" },
2064 { 0x76, "AT91SAM7SLxx Series" },
2065 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2066 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2067 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2068 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2069 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2070 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2071 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2072 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2073 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2074 { 0x92, "AT91x92 Series" },
2075 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2076 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2077 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2078 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2079 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2080 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2081 { 0xA5, "ATSAM5A" },
2082 { 0xF0, "AT75Cxx Series" },
2083 { -1, NULL },
2084 };
2085
2086 static const char *const nvptype[] = {
2087 "rom", /* 0 */
2088 "romless or onchip flash", /* 1 */
2089 "embedded flash memory",/* 2 */
2090 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2091 "sram emulating flash", /* 4 */
2092 _unknown, /* 5 */
2093 _unknown, /* 6 */
2094 _unknown, /* 7 */
2095 };
2096
2097 static const char *_yes_or_no(uint32_t v)
2098 {
2099 if (v)
2100 return "YES";
2101 else
2102 return "NO";
2103 }
2104
2105 static const char *const _rc_freq[] = {
2106 "4 MHz", "8 MHz", "12 MHz", "reserved"
2107 };
2108
2109 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
2110 {
2111 uint32_t v;
2112 uint32_t rcen;
2113
2114 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2115 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2116 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2117 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2118 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2119 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2120 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2121 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2122
2123 pChip->cfg.rc_freq = 0;
2124 if (rcen) {
2125 switch (v) {
2126 default:
2127 pChip->cfg.rc_freq = 0;
2128 break;
2129 case 0:
2130 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2131 break;
2132 case 1:
2133 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2134 break;
2135 case 2:
2136 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2137 break;
2138 }
2139 }
2140
2141 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2142 LOG_USER("(startup clks, time= %f uSecs)",
2143 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2144 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2145 LOG_USER("(mainosc source: %s)",
2146 v ? "external xtal" : "internal RC");
2147
2148 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2149 LOG_USER("(clock failure enabled: %s)",
2150 _yes_or_no(v));
2151 }
2152
2153 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
2154 {
2155 int x;
2156 uint32_t v;
2157 const char *cp;
2158
2159 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2160 LOG_USER_N("\n");
2161
2162 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2163 LOG_USER("%s", eproc_names[v]);
2164
2165 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2166 LOG_USER("%s", nvpsize[v]);
2167
2168 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2169 LOG_USER("%s", nvpsize2[v]);
2170
2171 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2172 LOG_USER("%s", sramsize[v]);
2173
2174 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2175 cp = _unknown;
2176 for (x = 0; archnames[x].name; x++) {
2177 if (v == archnames[x].value) {
2178 cp = archnames[x].name;
2179 break;
2180 }
2181 }
2182
2183 LOG_USER("%s", cp);
2184
2185 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2186 LOG_USER("%s", nvptype[v]);
2187
2188 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2189 LOG_USER("(exists: %s)", _yes_or_no(v));
2190 }
2191
2192 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
2193 {
2194 uint32_t v;
2195
2196 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2197 LOG_USER("(main ready: %s)", _yes_or_no(v));
2198
2199 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2200
2201 v = (v * pChip->cfg.slow_freq) / 16;
2202 pChip->cfg.mainosc_freq = v;
2203
2204 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2205 _tomhz(v),
2206 (uint32_t)(pChip->cfg.slow_freq / 1000),
2207 (uint32_t)(pChip->cfg.slow_freq % 1000));
2208 }
2209
2210 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
2211 {
2212 uint32_t mula, diva;
2213
2214 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2215 LOG_USER_N("\n");
2216 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2217 LOG_USER_N("\n");
2218 pChip->cfg.plla_freq = 0;
2219 if (mula == 0)
2220 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2221 else if (diva == 0)
2222 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2223 else if (diva >= 1) {
2224 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2225 LOG_USER("\tPLLA Freq: %3.03f MHz",
2226 _tomhz(pChip->cfg.plla_freq));
2227 }
2228 }
2229
2230 static void sam4_explain_mckr(struct sam4_chip *pChip)
2231 {
2232 uint32_t css, pres, fin = 0;
2233 int pdiv = 0;
2234 const char *cp = NULL;
2235
2236 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2237 switch (css & 3) {
2238 case 0:
2239 fin = pChip->cfg.slow_freq;
2240 cp = "slowclk";
2241 break;
2242 case 1:
2243 fin = pChip->cfg.mainosc_freq;
2244 cp = "mainosc";
2245 break;
2246 case 2:
2247 fin = pChip->cfg.plla_freq;
2248 cp = "plla";
2249 break;
2250 case 3:
2251 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2252 fin = 480 * 1000 * 1000;
2253 cp = "upll";
2254 } else {
2255 fin = 0;
2256 cp = "upll (*ERROR* UPLL is disabled)";
2257 }
2258 break;
2259 default:
2260 assert(0);
2261 break;
2262 }
2263
2264 LOG_USER("%s (%3.03f Mhz)",
2265 cp,
2266 _tomhz(fin));
2267 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2268 switch (pres & 0x07) {
2269 case 0:
2270 pdiv = 1;
2271 cp = "selected clock";
2272 break;
2273 case 1:
2274 pdiv = 2;
2275 cp = "clock/2";
2276 break;
2277 case 2:
2278 pdiv = 4;
2279 cp = "clock/4";
2280 break;
2281 case 3:
2282 pdiv = 8;
2283 cp = "clock/8";
2284 break;
2285 case 4:
2286 pdiv = 16;
2287 cp = "clock/16";
2288 break;
2289 case 5:
2290 pdiv = 32;
2291 cp = "clock/32";
2292 break;
2293 case 6:
2294 pdiv = 64;
2295 cp = "clock/64";
2296 break;
2297 case 7:
2298 pdiv = 6;
2299 cp = "clock/6";
2300 break;
2301 default:
2302 assert(0);
2303 break;
2304 }
2305 LOG_USER("(%s)", cp);
2306 fin = fin / pdiv;
2307 /* sam4 has a *SINGLE* clock - */
2308 /* other at91 series parts have divisors for these. */
2309 pChip->cfg.cpu_freq = fin;
2310 pChip->cfg.mclk_freq = fin;
2311 pChip->cfg.fclk_freq = fin;
2312 LOG_USER("\t\tResult CPU Freq: %3.03f",
2313 _tomhz(fin));
2314 }
2315
2316 #if 0
2317 static struct sam4_chip *target2sam4(struct target *pTarget)
2318 {
2319 struct sam4_chip *pChip;
2320
2321 if (pTarget == NULL)
2322 return NULL;
2323
2324 pChip = all_sam4_chips;
2325 while (pChip) {
2326 if (pChip->target == pTarget)
2327 break; /* return below */
2328 else
2329 pChip = pChip->next;
2330 }
2331 return pChip;
2332 }
2333 #endif
2334
2335 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
2336 {
2337 /* this function exists to help */
2338 /* keep funky offsetof() errors */
2339 /* and casting from causing bugs */
2340
2341 /* By using prototypes - we can detect what would */
2342 /* be casting errors. */
2343
2344 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2345 }
2346
2347
2348 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2349 struct sam4_cfg, \
2350 NAME), # NAME, FUNC }
2351 static const struct sam4_reg_list sam4_all_regs[] = {
2352 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2353 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2354 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2355 SAM4_ENTRY(CKGR_UCKR, NULL),
2356 SAM4_ENTRY(PMC_FSMR, NULL),
2357 SAM4_ENTRY(PMC_FSPR, NULL),
2358 SAM4_ENTRY(PMC_IMR, NULL),
2359 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2360 SAM4_ENTRY(PMC_PCK0, NULL),
2361 SAM4_ENTRY(PMC_PCK1, NULL),
2362 SAM4_ENTRY(PMC_PCK2, NULL),
2363 SAM4_ENTRY(PMC_PCSR, NULL),
2364 SAM4_ENTRY(PMC_SCSR, NULL),
2365 SAM4_ENTRY(PMC_SR, NULL),
2366 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2367 SAM4_ENTRY(CHIPID_EXID, NULL),
2368 /* TERMINATE THE LIST */
2369 { .name = NULL }
2370 };
2371 #undef SAM4_ENTRY
2372
2373 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2374 {
2375 return bank->driver_priv;
2376 }
2377
2378 /**
2379 * Given a pointer to where it goes in the structure,
2380 * determine the register name, address from the all registers table.
2381 */
2382 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
2383 {
2384 const struct sam4_reg_list *pReg;
2385
2386 pReg = &(sam4_all_regs[0]);
2387 while (pReg->name) {
2388 uint32_t *pPossible;
2389
2390 /* calculate where this one go.. */
2391 /* it is "possibly" this register. */
2392
2393 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2394
2395 /* well? Is it this register */
2396 if (pPossible == goes_here) {
2397 /* Jump for joy! */
2398 return pReg;
2399 }
2400
2401 /* next... */
2402 pReg++;
2403 }
2404 /* This is *TOTAL*PANIC* - we are totally screwed. */
2405 LOG_ERROR("INVALID SAM4 REGISTER");
2406 return NULL;
2407 }
2408
2409 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
2410 {
2411 const struct sam4_reg_list *pReg;
2412 int r;
2413
2414 pReg = sam4_GetReg(pChip, goes_here);
2415 if (!pReg)
2416 return ERROR_FAIL;
2417
2418 r = target_read_u32(pChip->target, pReg->address, goes_here);
2419 if (r != ERROR_OK) {
2420 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2421 pReg->name, (unsigned)(pReg->address), r);
2422 }
2423 return r;
2424 }
2425
2426 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
2427 {
2428 int r;
2429 const struct sam4_reg_list *pReg;
2430
2431 pReg = &(sam4_all_regs[0]);
2432 while (pReg->name) {
2433 r = sam4_ReadThisReg(pChip,
2434 sam4_get_reg_ptr(&(pChip->cfg), pReg));
2435 if (r != ERROR_OK) {
2436 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2437 pReg->name, ((unsigned)(pReg->address)), r);
2438 return r;
2439 }
2440 pReg++;
2441 }
2442
2443 return ERROR_OK;
2444 }
2445
2446 static int sam4_GetInfo(struct sam4_chip *pChip)
2447 {
2448 const struct sam4_reg_list *pReg;
2449 uint32_t regval;
2450 int r;
2451
2452 r = sam4_ReadAllRegs(pChip);
2453 if (r != ERROR_OK)
2454 return r;
2455
2456 pReg = &(sam4_all_regs[0]);
2457 while (pReg->name) {
2458 /* display all regs */
2459 LOG_DEBUG("Start: %s", pReg->name);
2460 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
2461 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2462 REG_NAME_WIDTH,
2463 pReg->name,
2464 pReg->address,
2465 regval);
2466 if (pReg->explain_func)
2467 (*(pReg->explain_func))(pChip);
2468 LOG_DEBUG("End: %s", pReg->name);
2469 pReg++;
2470 }
2471 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2472 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2473 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2474 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2475 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2476
2477 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2478 pChip->cfg.unique_id[0],
2479 pChip->cfg.unique_id[1],
2480 pChip->cfg.unique_id[2],
2481 pChip->cfg.unique_id[3]);
2482
2483 return ERROR_OK;
2484 }
2485
2486 static int sam4_protect_check(struct flash_bank *bank)
2487 {
2488 int r;
2489 uint32_t v[4] = {0};
2490 unsigned x;
2491 struct sam4_bank_private *pPrivate;
2492
2493 LOG_DEBUG("Begin");
2494 if (bank->target->state != TARGET_HALTED) {
2495 LOG_ERROR("Target not halted");
2496 return ERROR_TARGET_NOT_HALTED;
2497 }
2498
2499 pPrivate = get_sam4_bank_private(bank);
2500 if (!pPrivate) {
2501 LOG_ERROR("no private for this bank?");
2502 return ERROR_FAIL;
2503 }
2504 if (!(pPrivate->probed))
2505 return ERROR_FLASH_BANK_NOT_PROBED;
2506
2507 r = FLASHD_GetLockBits(pPrivate, v);
2508 if (r != ERROR_OK) {
2509 LOG_DEBUG("Failed: %d", r);
2510 return r;
2511 }
2512
2513 for (x = 0; x < pPrivate->nsectors; x++)
2514 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2515 LOG_DEBUG("Done");
2516 return ERROR_OK;
2517 }
2518
2519 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2520 {
2521 struct sam4_chip *pChip;
2522
2523 pChip = all_sam4_chips;
2524
2525 /* is this an existing chip? */
2526 while (pChip) {
2527 if (pChip->target == bank->target)
2528 break;
2529 pChip = pChip->next;
2530 }
2531
2532 if (!pChip) {
2533 /* this is a *NEW* chip */
2534 pChip = calloc(1, sizeof(struct sam4_chip));
2535 if (!pChip) {
2536 LOG_ERROR("NO RAM!");
2537 return ERROR_FAIL;
2538 }
2539 pChip->target = bank->target;
2540 /* insert at head */
2541 pChip->next = all_sam4_chips;
2542 all_sam4_chips = pChip;
2543 pChip->target = bank->target;
2544 /* assumption is this runs at 32khz */
2545 pChip->cfg.slow_freq = 32768;
2546 pChip->probed = false;
2547 }
2548
2549 switch (bank->base) {
2550 default:
2551 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2552 "[at91sam4s series] )",
2553 ((unsigned int)(bank->base)),
2554 ((unsigned int)(FLASH_BANK_BASE_S)));
2555 return ERROR_FAIL;
2556
2557 /* at91sam4s series only has bank 0*/
2558 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2559 case FLASH_BANK_BASE_S:
2560 case FLASH_BANK_BASE_C:
2561 bank->driver_priv = &(pChip->details.bank[0]);
2562 bank->bank_number = 0;
2563 pChip->details.bank[0].pChip = pChip;
2564 pChip->details.bank[0].pBank = bank;
2565 break;
2566
2567 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2568 case FLASH_BANK1_BASE_1024K_SD:
2569 case FLASH_BANK1_BASE_2048K_SD:
2570 case FLASH_BANK1_BASE_C32:
2571 bank->driver_priv = &(pChip->details.bank[1]);
2572 bank->bank_number = 1;
2573 pChip->details.bank[1].pChip = pChip;
2574 pChip->details.bank[1].pBank = bank;
2575 break;
2576 }
2577
2578 /* we initialize after probing. */
2579 return ERROR_OK;
2580 }
2581
2582 /**
2583 * Remove all chips from the internal list without distinguishing which one
2584 * is owned by this bank. This simplification works only for one shot
2585 * deallocation like current flash_free_all_banks()
2586 */
2587 static void sam4_free_driver_priv(struct flash_bank *bank)
2588 {
2589 struct sam4_chip *chip = all_sam4_chips;
2590 while (chip) {
2591 struct sam4_chip *next = chip->next;
2592 free(chip);
2593 chip = next;
2594 }
2595 all_sam4_chips = NULL;
2596 }
2597
2598 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2599 {
2600 const struct sam4_chip_details *pDetails;
2601 struct sam4_chip *pChip;
2602 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2603 unsigned x;
2604
2605 LOG_DEBUG("Begin");
2606 pDetails = all_sam4_details;
2607 while (pDetails->name) {
2608 /* Compare cidr without version bits */
2609 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2610 break;
2611 else
2612 pDetails++;
2613 }
2614 if (pDetails->name == NULL) {
2615 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2616 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2617 /* Help the victim, print details about the chip */
2618 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2619 pPrivate->pChip->cfg.CHIPID_CIDR);
2620 sam4_explain_chipid_cidr(pPrivate->pChip);
2621 return ERROR_FAIL;
2622 } else {
2623 LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, pDetails->name, pDetails->chipid_cidr);
2624 }
2625
2626 /* DANGER: THERE ARE DRAGONS HERE */
2627
2628 /* get our pChip - it is going */
2629 /* to be over-written shortly */
2630 pChip = pPrivate->pChip;
2631
2632 /* Note that, in reality: */
2633 /* */
2634 /* pPrivate = &(pChip->details.bank[0]) */
2635 /* or pPrivate = &(pChip->details.bank[1]) */
2636 /* */
2637
2638 /* save the "bank" pointers */
2639 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2640 saved_banks[x] = pChip->details.bank[x].pBank;
2641
2642 /* Overwrite the "details" structure. */
2643 memcpy(&(pPrivate->pChip->details),
2644 pDetails,
2645 sizeof(pPrivate->pChip->details));
2646
2647 /* now fix the ghosted pointers */
2648 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2649 pChip->details.bank[x].pChip = pChip;
2650 pChip->details.bank[x].pBank = saved_banks[x];
2651 }
2652
2653 /* update the *BANK*SIZE* */
2654
2655 LOG_DEBUG("End");
2656 return ERROR_OK;
2657 }
2658
2659 static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
2660 {
2661 struct sam4_bank_private *pPrivate;
2662 int k = bank->size / 1024;
2663
2664 pPrivate = get_sam4_bank_private(bank);
2665 if (pPrivate == NULL) {
2666 buf[0] = '\0';
2667 return ERROR_FAIL;
2668 }
2669
2670 snprintf(buf, buf_size,
2671 "%s bank %d: %d kB at " TARGET_ADDR_FMT,
2672 pPrivate->pChip->details.name,
2673 pPrivate->bank_number,
2674 k,
2675 bank->base);
2676
2677 return ERROR_OK;
2678 }
2679
2680 static int sam4_probe(struct flash_bank *bank)
2681 {
2682 int r;
2683 struct sam4_bank_private *pPrivate;
2684
2685
2686 LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
2687 if (bank->target->state != TARGET_HALTED) {
2688 LOG_ERROR("Target not halted");
2689 return ERROR_TARGET_NOT_HALTED;
2690 }
2691
2692 pPrivate = get_sam4_bank_private(bank);
2693 if (!pPrivate) {
2694 LOG_ERROR("Invalid/unknown bank number");
2695 return ERROR_FAIL;
2696 }
2697
2698 r = sam4_ReadAllRegs(pPrivate->pChip);
2699 if (r != ERROR_OK)
2700 return r;
2701
2702 LOG_DEBUG("Here");
2703 if (pPrivate->pChip->probed)
2704 r = sam4_GetInfo(pPrivate->pChip);
2705 else
2706 r = sam4_GetDetails(pPrivate);
2707 if (r != ERROR_OK)
2708 return r;
2709
2710 /* update the flash bank size */
2711 for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2712 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2713 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2714 LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
2715 TARGET_ADDR_FMT ", idx %d", bank->base,
2716 bank->base + bank->size, x);
2717 break;
2718 }
2719 }
2720
2721 if (bank->sectors == NULL) {
2722 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2723 if (bank->sectors == NULL) {
2724 LOG_ERROR("No memory!");
2725 return ERROR_FAIL;
2726 }
2727 bank->num_sectors = pPrivate->nsectors;
2728
2729 for (unsigned int x = 0; x < bank->num_sectors; x++) {
2730 bank->sectors[x].size = pPrivate->sector_size;
2731 bank->sectors[x].offset = x * (pPrivate->sector_size);
2732 /* mark as unknown */
2733 bank->sectors[x].is_erased = -1;
2734 bank->sectors[x].is_protected = -1;
2735 }
2736 }
2737
2738 pPrivate->probed = true;
2739
2740 r = sam4_protect_check(bank);
2741 if (r != ERROR_OK)
2742 return r;
2743
2744 LOG_DEBUG("Bank = %d, nbanks = %d",
2745 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2746 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2747 /* read unique id, */
2748 /* it appears to be associated with the *last* flash bank. */
2749 FLASHD_ReadUniqueID(pPrivate);
2750 }
2751
2752 return r;
2753 }
2754
2755 static int sam4_auto_probe(struct flash_bank *bank)
2756 {
2757 struct sam4_bank_private *pPrivate;
2758
2759 pPrivate = get_sam4_bank_private(bank);
2760 if (pPrivate && pPrivate->probed)
2761 return ERROR_OK;
2762
2763 return sam4_probe(bank);
2764 }
2765
2766 static int sam4_erase(struct flash_bank *bank, unsigned int first,
2767 unsigned int last)
2768 {
2769 struct sam4_bank_private *pPrivate;
2770 int r;
2771 int pageCount;
2772 /*16 pages equals 8KB - Same size as a lock region*/
2773 pageCount = 16;
2774 uint32_t status;
2775
2776 LOG_DEBUG("Here");
2777 if (bank->target->state != TARGET_HALTED) {
2778 LOG_ERROR("Target not halted");
2779 return ERROR_TARGET_NOT_HALTED;
2780 }
2781
2782 r = sam4_auto_probe(bank);
2783 if (r != ERROR_OK) {
2784 LOG_DEBUG("Here,r=%d", r);
2785 return r;
2786 }
2787
2788 pPrivate = get_sam4_bank_private(bank);
2789 if (!(pPrivate->probed))
2790 return ERROR_FLASH_BANK_NOT_PROBED;
2791
2792 if ((first == 0) && ((last + 1) == pPrivate->nsectors)) {
2793 /* whole chip */
2794 LOG_DEBUG("Here");
2795 return FLASHD_EraseEntireBank(pPrivate);
2796 }
2797 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2798 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
2799 for (unsigned int i = first; i <= last; i++) {
2800 /*16 pages equals 8KB - Same size as a lock region*/
2801 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2802 LOG_INFO("Erasing sector: 0x%08x", i);
2803 if (r != ERROR_OK)
2804 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2805 i);
2806 if (status & (1 << 2)) {
2807 LOG_ERROR("SAM4: Lock Region %u is locked", i);
2808 return ERROR_FAIL;
2809 }
2810 if (status & (1 << 1)) {
2811 LOG_ERROR("SAM4: Flash Command error @lock region %u", i);
2812 return ERROR_FAIL;
2813 }
2814 }
2815
2816 return ERROR_OK;
2817 }
2818
2819 static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
2820 unsigned int last)
2821 {
2822 struct sam4_bank_private *pPrivate;
2823 int r;
2824
2825 LOG_DEBUG("Here");
2826 if (bank->target->state != TARGET_HALTED) {
2827 LOG_ERROR("Target not halted");
2828 return ERROR_TARGET_NOT_HALTED;
2829 }
2830
2831 pPrivate = get_sam4_bank_private(bank);
2832 if (!(pPrivate->probed))
2833 return ERROR_FLASH_BANK_NOT_PROBED;
2834
2835 if (set)
2836 r = FLASHD_Lock(pPrivate, first, last);
2837 else
2838 r = FLASHD_Unlock(pPrivate, first, last);
2839 LOG_DEBUG("End: r=%d", r);
2840
2841 return r;
2842
2843 }
2844
2845 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2846 {
2847 uint32_t adr;
2848 int r;
2849
2850 adr = pagenum * pPrivate->page_size;
2851 adr = adr + pPrivate->base_address;
2852
2853 r = target_read_memory(pPrivate->pChip->target,
2854 adr,
2855 4, /* THIS*MUST*BE* in 32bit values */
2856 pPrivate->page_size / 4,
2857 buf);
2858 if (r != ERROR_OK)
2859 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2860 (unsigned int)(adr));
2861 return r;
2862 }
2863
2864 static int sam4_set_wait(struct sam4_bank_private *pPrivate)
2865 {
2866 uint32_t fmr; /* EEFC Flash Mode Register */
2867 int r;
2868
2869 /* Get flash mode register value */
2870 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2871 if (r != ERROR_OK) {
2872 LOG_ERROR("Error Read failed: read flash mode register");
2873 return r;
2874 }
2875
2876 /* Clear flash wait state field */
2877 fmr &= 0xfffff0ff;
2878
2879 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2880 fmr |= (pPrivate->flash_wait_states << 8);
2881
2882 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2883 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2884 if (r != ERROR_OK)
2885 LOG_ERROR("Error Write failed: set flash mode register");
2886
2887 return r;
2888 }
2889
2890 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2891 {
2892 uint32_t adr;
2893 uint32_t status;
2894 int r;
2895
2896 adr = pagenum * pPrivate->page_size;
2897 adr = (adr + pPrivate->base_address);
2898
2899 /* 1st sector 8kBytes - page 0 - 15*/
2900 /* 2nd sector 8kBytes - page 16 - 30*/
2901 /* 3rd sector 48kBytes - page 31 - 127*/
2902 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2903 r = target_write_memory(pPrivate->pChip->target,
2904 adr,
2905 4, /* THIS*MUST*BE* in 32bit values */
2906 pPrivate->page_size / 4,
2907 buf);
2908 if (r != ERROR_OK) {
2909 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2910 (unsigned int)(adr));
2911 return r;
2912 }
2913
2914 r = EFC_PerformCommand(pPrivate,
2915 /* send Erase & Write Page */
2916 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2917 pagenum,
2918 &status);
2919
2920 if (r != ERROR_OK)
2921 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2922 (unsigned int)(adr));
2923 if (status & (1 << 2)) {
2924 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2925 return ERROR_FAIL;
2926 }
2927 if (status & (1 << 1)) {
2928 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2929 return ERROR_FAIL;
2930 }
2931 return ERROR_OK;
2932 }
2933
2934 static int sam4_write(struct flash_bank *bank,
2935 const uint8_t *buffer,
2936 uint32_t offset,
2937 uint32_t count)
2938 {
2939 int n;
2940 unsigned page_cur;
2941 unsigned page_end;
2942 int r;
2943 unsigned page_offset;
2944 struct sam4_bank_private *pPrivate;
2945 uint8_t *pagebuffer;
2946
2947 /* in case we bail further below, set this to null */
2948 pagebuffer = NULL;
2949
2950 /* ignore dumb requests */
2951 if (count == 0) {
2952 r = ERROR_OK;
2953 goto done;
2954 }
2955
2956 if (bank->target->state != TARGET_HALTED) {
2957 LOG_ERROR("Target not halted");
2958 r = ERROR_TARGET_NOT_HALTED;
2959 goto done;
2960 }
2961
2962 pPrivate = get_sam4_bank_private(bank);
2963 if (!(pPrivate->probed)) {
2964 r = ERROR_FLASH_BANK_NOT_PROBED;
2965 goto done;
2966 }
2967
2968 if ((offset + count) > pPrivate->size_bytes) {
2969 LOG_ERROR("Flash write error - past end of bank");
2970 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2971 (unsigned int)(offset),
2972 (unsigned int)(count),
2973 (unsigned int)(pPrivate->size_bytes));
2974 r = ERROR_FAIL;
2975 goto done;
2976 }
2977
2978 pagebuffer = malloc(pPrivate->page_size);
2979 if (!pagebuffer) {
2980 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2981 r = ERROR_FAIL;
2982 goto done;
2983 }
2984
2985 r = sam4_set_wait(pPrivate);
2986 if (r != ERROR_OK)
2987 goto done;
2988
2989 /* what page do we start & end in? */
2990 page_cur = offset / pPrivate->page_size;
2991 page_end = (offset + count - 1) / pPrivate->page_size;
2992
2993 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2994 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2995
2996 /* Special case: all one page */
2997 /* */
2998 /* Otherwise: */
2999 /* (1) non-aligned start */
3000 /* (2) body pages */
3001 /* (3) non-aligned end. */
3002
3003 /* Handle special case - all one page. */
3004 if (page_cur == page_end) {
3005 LOG_DEBUG("Special case, all in one page");
3006 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
3007 if (r != ERROR_OK)
3008 goto done;
3009
3010 page_offset = (offset & (pPrivate->page_size-1));
3011 memcpy(pagebuffer + page_offset,
3012 buffer,
3013 count);
3014
3015 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
3016 if (r != ERROR_OK)
3017 goto done;
3018 r = ERROR_OK;
3019 goto done;
3020 }
3021
3022 /* non-aligned start */
3023 page_offset = offset & (pPrivate->page_size - 1);
3024 if (page_offset) {
3025 LOG_DEBUG("Not-Aligned start");
3026 /* read the partial */
3027 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
3028 if (r != ERROR_OK)
3029 goto done;
3030
3031 /* over-write with new data */
3032 n = (pPrivate->page_size - page_offset);
3033 memcpy(pagebuffer + page_offset,
3034 buffer,
3035 n);
3036
3037 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
3038 if (r != ERROR_OK)
3039 goto done;
3040
3041 count -= n;
3042 offset += n;
3043 buffer += n;
3044 page_cur++;
3045 }
3046
3047 /* By checking that offset is correct here, we also
3048 fix a clang warning */
3049 assert(offset % pPrivate->page_size == 0);
3050
3051 /* intermediate large pages */
3052 /* also - the final *terminal* */
3053 /* if that terminal page is a full page */
3054 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3055 (int)page_cur, (int)page_end, (unsigned int)(count));
3056
3057 while ((page_cur < page_end) &&
3058 (count >= pPrivate->page_size)) {
3059 r = sam4_page_write(pPrivate, page_cur, buffer);
3060 if (r != ERROR_OK)
3061 goto done;
3062 count -= pPrivate->page_size;
3063 buffer += pPrivate->page_size;
3064 page_cur += 1;
3065 }
3066
3067 /* terminal partial page? */
3068 if (count) {
3069 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3070 /* we have a partial page */
3071 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
3072 if (r != ERROR_OK)
3073 goto done;
3074 /* data goes at start */
3075 memcpy(pagebuffer, buffer, count);
3076 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
3077 if (r != ERROR_OK)
3078 goto done;
3079 }
3080 LOG_DEBUG("Done!");
3081 r = ERROR_OK;
3082 done:
3083 free(pagebuffer);
3084 return r;
3085 }
3086
3087 COMMAND_HANDLER(sam4_handle_info_command)
3088 {
3089 struct sam4_chip *pChip;
3090 pChip = get_current_sam4(CMD);
3091 if (!pChip)
3092 return ERROR_OK;
3093
3094 unsigned x;
3095 int r;
3096
3097 /* bank0 must exist before we can do anything */
3098 if (pChip->details.bank[0].pBank == NULL) {
3099 x = 0;
3100 need_define:
3101 command_print(CMD,
3102 "Please define bank %d via command: flash bank %s ... ",
3103 x,
3104 at91sam4_flash.name);
3105 return ERROR_FAIL;
3106 }
3107
3108 /* if bank 0 is not probed, then probe it */
3109 if (!(pChip->details.bank[0].probed)) {
3110 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3111 if (r != ERROR_OK)
3112 return ERROR_FAIL;
3113 }
3114 /* above guarantees the "chip details" structure is valid */
3115 /* and thus, bank private areas are valid */
3116 /* and we have a SAM4 chip, what a concept! */
3117
3118 /* auto-probe other banks, 0 done above */
3119 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3120 /* skip banks not present */
3121 if (!(pChip->details.bank[x].present))
3122 continue;
3123
3124 if (pChip->details.bank[x].pBank == NULL)
3125 goto need_define;
3126
3127 if (pChip->details.bank[x].probed)
3128 continue;
3129
3130 r = sam4_auto_probe(pChip->details.bank[x].pBank);
3131 if (r != ERROR_OK)
3132 return r;
3133 }
3134
3135 r = sam4_GetInfo(pChip);
3136 if (r != ERROR_OK) {
3137 LOG_DEBUG("Sam4Info, Failed %d", r);
3138 return r;
3139 }
3140
3141 return ERROR_OK;
3142 }
3143
3144 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3145 {
3146 unsigned x, v;
3147 int r, who;
3148 struct sam4_chip *pChip;
3149
3150 pChip = get_current_sam4(CMD);
3151 if (!pChip)
3152 return ERROR_OK;
3153
3154 if (pChip->target->state != TARGET_HALTED) {
3155 LOG_ERROR("sam4 - target not halted");
3156 return ERROR_TARGET_NOT_HALTED;
3157 }
3158
3159 if (pChip->details.bank[0].pBank == NULL) {
3160 command_print(CMD, "Bank0 must be defined first via: flash bank %s ...",
3161 at91sam4_flash.name);
3162 return ERROR_FAIL;
3163 }
3164 if (!pChip->details.bank[0].probed) {
3165 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3166 if (r != ERROR_OK)
3167 return r;
3168 }
3169
3170 switch (CMD_ARGC) {
3171 default:
3172 return ERROR_COMMAND_SYNTAX_ERROR;
3173 case 0:
3174 goto showall;
3175 case 1:
3176 who = -1;
3177 break;
3178 case 2:
3179 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3180 who = -1;
3181 else {
3182 uint32_t v32;
3183 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3184 who = v32;
3185 }
3186 break;
3187 }
3188
3189 if (0 == strcmp("show", CMD_ARGV[0])) {
3190 if (who == -1) {
3191 showall:
3192 r = ERROR_OK;
3193 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3194 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3195 if (r != ERROR_OK)
3196 break;
3197 command_print(CMD, "sam4-gpnvm%u: %u", x, v);
3198 }
3199 return r;
3200 }
3201 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3202 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3203 if (r == ERROR_OK)
3204 command_print(CMD, "sam4-gpnvm%u: %u", who, v);
3205 return r;
3206 } else {
3207 command_print(CMD, "sam4-gpnvm invalid GPNVM: %u", who);
3208 return ERROR_COMMAND_SYNTAX_ERROR;
3209 }
3210 }
3211
3212 if (who == -1) {
3213 command_print(CMD, "Missing GPNVM number");
3214 return ERROR_COMMAND_SYNTAX_ERROR;
3215 }
3216
3217 if (0 == strcmp("set", CMD_ARGV[0]))
3218 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3219 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3220 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3221 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3222 else {
3223 command_print(CMD, "Unknown command: %s", CMD_ARGV[0]);
3224 r = ERROR_COMMAND_SYNTAX_ERROR;
3225 }
3226 return r;
3227 }
3228
3229 COMMAND_HANDLER(sam4_handle_slowclk_command)
3230 {
3231 struct sam4_chip *pChip;
3232
3233 pChip = get_current_sam4(CMD);
3234 if (!pChip)
3235 return ERROR_OK;
3236
3237 switch (CMD_ARGC) {
3238 case 0:
3239 /* show */
3240 break;
3241 case 1:
3242 {
3243 /* set */
3244 uint32_t v;
3245 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3246 if (v > 200000) {
3247 /* absurd slow clock of 200Khz? */
3248 command_print(CMD, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3249 return ERROR_COMMAND_SYNTAX_ERROR;
3250 }
3251 pChip->cfg.slow_freq = v;
3252 break;
3253 }
3254 default:
3255 /* error */
3256 command_print(CMD, "Too many parameters");
3257 return ERROR_COMMAND_SYNTAX_ERROR;
3258 }
3259 command_print(CMD, "Slowclk freq: %d.%03dkhz",
3260 (int)(pChip->cfg.slow_freq / 1000),
3261 (int)(pChip->cfg.slow_freq % 1000));
3262 return ERROR_OK;
3263 }
3264
3265 static const struct command_registration at91sam4_exec_command_handlers[] = {
3266 {
3267 .name = "gpnvm",
3268 .handler = sam4_handle_gpnvm_command,
3269 .mode = COMMAND_EXEC,
3270 .usage = "[('clr'|'set'|'show') bitnum]",
3271 .help = "Without arguments, shows all bits in the gpnvm "
3272 "register. Otherwise, clears, sets, or shows one "
3273 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3274 },
3275 {
3276 .name = "info",
3277 .handler = sam4_handle_info_command,
3278 .mode = COMMAND_EXEC,
3279 .help = "Print information about the current at91sam4 chip "
3280 "and its flash configuration.",
3281 .usage = "",
3282 },
3283 {
3284 .name = "slowclk",
3285 .handler = sam4_handle_slowclk_command,
3286 .mode = COMMAND_EXEC,
3287 .usage = "[clock_hz]",
3288 .help = "Display or set the slowclock frequency "
3289 "(default 32768 Hz).",
3290 },
3291 COMMAND_REGISTRATION_DONE
3292 };
3293 static const struct command_registration at91sam4_command_handlers[] = {
3294 {
3295 .name = "at91sam4",
3296 .mode = COMMAND_ANY,
3297 .help = "at91sam4 flash command group",
3298 .usage = "",
3299 .chain = at91sam4_exec_command_handlers,
3300 },
3301 COMMAND_REGISTRATION_DONE
3302 };
3303
3304 const struct flash_driver at91sam4_flash = {
3305 .name = "at91sam4",
3306 .commands = at91sam4_command_handlers,
3307 .flash_bank_command = sam4_flash_bank_command,
3308 .erase = sam4_erase,
3309 .protect = sam4_protect,
3310 .write = sam4_write,
3311 .read = default_flash_read,
3312 .probe = sam4_probe,
3313 .auto_probe = sam4_auto_probe,
3314 .erase_check = default_flash_blank_check,
3315 .protect_check = sam4_protect_check,
3316 .info = sam4_info,
3317 .free_driver_priv = sam4_free_driver_priv,
3318 };
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