1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
25 /* Some of the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
64 #include <helper/time_support.h>
66 #define REG_NAME_WIDTH (12)
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
106 extern const struct flash_driver at91sam4_flash
;
108 static float _tomhz(uint32_t freq_hz
)
112 f
= ((float)(freq_hz
)) / 1000000.0;
116 /* How the chip is configured. */
118 uint32_t unique_id
[4];
122 uint32_t mainosc_freq
;
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR
;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID
;
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
168 struct sam4_bank_private
{
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
176 /* so we can find the chip we belong to */
177 struct sam4_chip
*pChip
;
178 /* so we can find the original bank pointer */
179 struct flash_bank
*pBank
;
180 unsigned bank_number
;
181 uint32_t controller_address
;
182 uint32_t base_address
;
183 uint32_t flash_wait_states
;
187 unsigned sector_size
;
191 struct sam4_chip_details
{
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr
;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm
[SAM4_N_NVM_BITS
];
205 unsigned total_flash_size
;
206 unsigned total_sram_size
;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank
[SAM4_MAX_FLASH_BANKS
];
214 struct sam4_chip
*next
;
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details
;
219 struct target
*target
;
224 struct sam4_reg_list
{
225 uint32_t address
; size_t struct_offset
; const char *name
;
226 void (*explain_func
)(struct sam4_chip
*pInfo
);
229 static struct sam4_chip
*all_sam4_chips
;
231 static struct sam4_chip
*get_current_sam4(struct command_invocation
*cmd
)
234 static struct sam4_chip
*p
;
236 t
= get_current_target(cmd
->ctx
);
238 command_print(cmd
, "No current target?");
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd
, "No SAM4 chips exist?");
255 command_print(cmd
, "Cannot find SAM4 chip?");
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details
[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
269 .chipid_cidr
= 0xA66D0EE0,
270 .name
= "at91sam4c32e",
271 .total_flash_size
= 2024 * 1024,
272 .total_sram_size
= 256 * 1024,
282 .base_address
= FLASH_BANK0_BASE_C32
,
283 .controller_address
= 0x400e0a00,
284 .flash_wait_states
= 5,
286 .size_bytes
= 1024 * 1024,
297 .base_address
= FLASH_BANK1_BASE_C32
,
298 .controller_address
= 0x400e0c00,
299 .flash_wait_states
= 5,
301 .size_bytes
= 1024 * 1024,
308 /* at91sam4c32c - LQFP100 */
310 .chipid_cidr
= 0xA64D0EE0,
311 .name
= "at91sam4c32c",
312 .total_flash_size
= 2024 * 1024,
313 .total_sram_size
= 256 * 1024,
323 .base_address
= FLASH_BANK0_BASE_C32
,
324 .controller_address
= 0x400e0a00,
325 .flash_wait_states
= 5,
327 .size_bytes
= 1024 * 1024,
338 .base_address
= FLASH_BANK1_BASE_C32
,
339 .controller_address
= 0x400e0c00,
340 .flash_wait_states
= 5,
342 .size_bytes
= 1024 * 1024,
349 /* at91sam4c16c - LQFP100 */
351 .chipid_cidr
= 0xA64C0CE0,
352 .name
= "at91sam4c16c",
353 .total_flash_size
= 1024 * 1024,
354 .total_sram_size
= 128 * 1024,
364 .base_address
= FLASH_BANK_BASE_C
,
365 .controller_address
= 0x400e0a00,
366 .flash_wait_states
= 5,
368 .size_bytes
= 1024 * 1024,
382 /* at91sam4c8c - LQFP100 */
384 .chipid_cidr
= 0xA64C0AE0,
385 .name
= "at91sam4c8c",
386 .total_flash_size
= 512 * 1024,
387 .total_sram_size
= 128 * 1024,
397 .base_address
= FLASH_BANK_BASE_C
,
398 .controller_address
= 0x400e0a00,
399 .flash_wait_states
= 5,
401 .size_bytes
= 512 * 1024,
415 /* at91sam4c4c (rev B) - LQFP100 */
417 .chipid_cidr
= 0xA64C0CE5,
418 .name
= "at91sam4c4c",
419 .total_flash_size
= 256 * 1024,
420 .total_sram_size
= 128 * 1024,
430 .base_address
= FLASH_BANK_BASE_C
,
431 .controller_address
= 0x400e0a00,
432 .flash_wait_states
= 5,
434 .size_bytes
= 256 * 1024,
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
452 .chipid_cidr
= 0xA3CC0CE0,
453 .name
= "at91sam4e16e",
454 .total_flash_size
= 1024 * 1024,
455 .total_sram_size
= 128 * 1024,
465 .base_address
= FLASH_BANK_BASE_S
,
466 .controller_address
= 0x400e0a00,
467 .flash_wait_states
= 5,
469 .size_bytes
= 1024 * 1024,
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
487 .chipid_cidr
= 0x293B0AE0,
488 .name
= "at91sam4n8a",
489 .total_flash_size
= 512 * 1024,
490 .total_sram_size
= 64 * 1024,
500 .base_address
= FLASH_BANK_BASE_S
,
501 .controller_address
= 0x400e0a00,
502 .flash_wait_states
= 5,
504 .size_bytes
= 512 * 1024,
518 /*atsam4n8b - LQFP64/QFN64*/
520 .chipid_cidr
= 0x294B0AE0,
521 .name
= "at91sam4n8b",
522 .total_flash_size
= 512 * 1024,
523 .total_sram_size
= 64 * 1024,
533 .base_address
= FLASH_BANK_BASE_S
,
534 .controller_address
= 0x400e0a00,
535 .flash_wait_states
= 5,
537 .size_bytes
= 512 * 1024,
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
553 .chipid_cidr
= 0x295B0AE0,
554 .name
= "at91sam4n8c",
555 .total_flash_size
= 512 * 1024,
556 .total_sram_size
= 64 * 1024,
566 .base_address
= FLASH_BANK_BASE_S
,
567 .controller_address
= 0x400e0a00,
568 .flash_wait_states
= 5,
570 .size_bytes
= 512 * 1024,
584 /*atsam4n16b - LQFP64/QFN64*/
586 .chipid_cidr
= 0x29460CE0,
587 .name
= "at91sam4n16b",
588 .total_flash_size
= 1024 * 1024,
589 .total_sram_size
= 80 * 1024,
599 .base_address
= FLASH_BANK_BASE_S
,
600 .controller_address
= 0x400e0a00,
601 .flash_wait_states
= 5,
603 .size_bytes
= 1024 * 1024,
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
619 .chipid_cidr
= 0x29560CE0,
620 .name
= "at91sam4n16c",
621 .total_flash_size
= 1024 * 1024,
622 .total_sram_size
= 80 * 1024,
632 .base_address
= FLASH_BANK_BASE_S
,
633 .controller_address
= 0x400e0a00,
634 .flash_wait_states
= 5,
636 .size_bytes
= 1024 * 1024,
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
654 .chipid_cidr
= 0x28AC0CE0,
655 .name
= "at91sam4s16c",
656 .total_flash_size
= 1024 * 1024,
657 .total_sram_size
= 128 * 1024,
667 .base_address
= FLASH_BANK_BASE_S
,
668 .controller_address
= 0x400e0a00,
669 .flash_wait_states
= 5,
671 .size_bytes
= 1024 * 1024,
685 /*at91sam4sa16c - TFBGA100/VFBGA100/LQFP100*/
687 .chipid_cidr
= 0x28a70ce0,
688 .name
= "at91sam4sa16c",
689 .total_flash_size
= 1024 * 1024,
690 .total_sram_size
= 160 * 1024,
701 .base_address
= FLASH_BANK_BASE_S
,
702 .controller_address
= 0x400e0a00,
703 .flash_wait_states
= 5,
705 .size_bytes
= 1024 * 1024,
719 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
721 .chipid_cidr
= 0x289C0CE0,
722 .name
= "at91sam4s16b",
723 .total_flash_size
= 1024 * 1024,
724 .total_sram_size
= 128 * 1024,
734 .base_address
= FLASH_BANK_BASE_S
,
735 .controller_address
= 0x400e0a00,
736 .flash_wait_states
= 5,
738 .size_bytes
= 1024 * 1024,
752 /*atsam4sa16b - LQFP64/QFN64*/
754 .chipid_cidr
= 0x28970CE0,
755 .name
= "at91sam4sa16b",
756 .total_flash_size
= 1024 * 1024,
757 .total_sram_size
= 160 * 1024,
767 .base_address
= FLASH_BANK_BASE_S
,
768 .controller_address
= 0x400e0a00,
769 .flash_wait_states
= 5,
771 .size_bytes
= 1024 * 1024,
785 /*atsam4s16a - LQFP48/QFN48*/
787 .chipid_cidr
= 0x288C0CE0,
788 .name
= "at91sam4s16a",
789 .total_flash_size
= 1024 * 1024,
790 .total_sram_size
= 128 * 1024,
800 .base_address
= FLASH_BANK_BASE_S
,
801 .controller_address
= 0x400e0a00,
802 .flash_wait_states
= 5,
804 .size_bytes
= 1024 * 1024,
818 /*atsam4s8c - LQFP100/BGA100*/
820 .chipid_cidr
= 0x28AC0AE0,
821 .name
= "at91sam4s8c",
822 .total_flash_size
= 512 * 1024,
823 .total_sram_size
= 128 * 1024,
833 .base_address
= FLASH_BANK_BASE_S
,
834 .controller_address
= 0x400e0a00,
835 .flash_wait_states
= 5,
837 .size_bytes
= 512 * 1024,
851 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
853 .chipid_cidr
= 0x289C0AE0,
854 .name
= "at91sam4s8b",
855 .total_flash_size
= 512 * 1024,
856 .total_sram_size
= 128 * 1024,
866 .base_address
= FLASH_BANK_BASE_S
,
867 .controller_address
= 0x400e0a00,
868 .flash_wait_states
= 5,
870 .size_bytes
= 512 * 1024,
884 /*atsam4s8a - LQFP48/BGA48*/
886 .chipid_cidr
= 0x288C0AE0,
887 .name
= "at91sam4s8a",
888 .total_flash_size
= 512 * 1024,
889 .total_sram_size
= 128 * 1024,
899 .base_address
= FLASH_BANK_BASE_S
,
900 .controller_address
= 0x400e0a00,
901 .flash_wait_states
= 5,
903 .size_bytes
= 512 * 1024,
918 /*atsam4s4c - LQFP100/BGA100*/
920 .chipid_cidr
= 0x28ab09e0,
921 .name
= "at91sam4s4c",
922 .total_flash_size
= 256 * 1024,
923 .total_sram_size
= 64 * 1024,
933 .base_address
= FLASH_BANK_BASE_S
,
934 .controller_address
= 0x400e0a00,
935 .flash_wait_states
= 5,
937 .size_bytes
= 256 * 1024,
952 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
954 .chipid_cidr
= 0x289b09e0,
955 .name
= "at91sam4s4b",
956 .total_flash_size
= 256 * 1024,
957 .total_sram_size
= 64 * 1024,
967 .base_address
= FLASH_BANK_BASE_S
,
968 .controller_address
= 0x400e0a00,
969 .flash_wait_states
= 5,
971 .size_bytes
= 256 * 1024,
986 /*atsam4s4a - LQFP48/QFN48*/
988 .chipid_cidr
= 0x288b09e0,
989 .name
= "at91sam4s4a",
990 .total_flash_size
= 256 * 1024,
991 .total_sram_size
= 64 * 1024,
1001 .base_address
= FLASH_BANK_BASE_S
,
1002 .controller_address
= 0x400e0a00,
1003 .flash_wait_states
= 5,
1005 .size_bytes
= 256 * 1024,
1007 .sector_size
= 8192,
1020 /*atsam4s2c - LQFP100/BGA100*/
1022 .chipid_cidr
= 0x28ab07e0,
1023 .name
= "at91sam4s2c",
1024 .total_flash_size
= 128 * 1024,
1025 .total_sram_size
= 64 * 1024,
1035 .base_address
= FLASH_BANK_BASE_S
,
1036 .controller_address
= 0x400e0a00,
1037 .flash_wait_states
= 5,
1039 .size_bytes
= 128 * 1024,
1041 .sector_size
= 8192,
1054 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1056 .chipid_cidr
= 0x289b07e0,
1057 .name
= "at91sam4s2b",
1058 .total_flash_size
= 128 * 1024,
1059 .total_sram_size
= 64 * 1024,
1069 .base_address
= FLASH_BANK_BASE_S
,
1070 .controller_address
= 0x400e0a00,
1071 .flash_wait_states
= 5,
1073 .size_bytes
= 128 * 1024,
1075 .sector_size
= 8192,
1088 /*atsam4s2a - LQFP48/QFN48*/
1090 .chipid_cidr
= 0x288b07e0,
1091 .name
= "at91sam4s2a",
1092 .total_flash_size
= 128 * 1024,
1093 .total_sram_size
= 64 * 1024,
1103 .base_address
= FLASH_BANK_BASE_S
,
1104 .controller_address
= 0x400e0a00,
1105 .flash_wait_states
= 5,
1107 .size_bytes
= 128 * 1024,
1109 .sector_size
= 8192,
1122 /*at91sam4sd32c - LQFP100/BGA100*/
1124 .chipid_cidr
= 0x29a70ee0,
1125 .name
= "at91sam4sd32c",
1126 .total_flash_size
= 2048 * 1024,
1127 .total_sram_size
= 160 * 1024,
1138 .base_address
= FLASH_BANK0_BASE_SD
,
1139 .controller_address
= 0x400e0a00,
1140 .flash_wait_states
= 5,
1142 .size_bytes
= 1024 * 1024,
1144 .sector_size
= 8192,
1154 .base_address
= FLASH_BANK1_BASE_2048K_SD
,
1155 .controller_address
= 0x400e0c00,
1156 .flash_wait_states
= 5,
1158 .size_bytes
= 1024 * 1024,
1160 .sector_size
= 8192,
1166 /*at91sam4sd32b - LQFP64/BGA64*/
1168 .chipid_cidr
= 0x29970ee0,
1169 .name
= "at91sam4sd32b",
1170 .total_flash_size
= 2048 * 1024,
1171 .total_sram_size
= 160 * 1024,
1182 .base_address
= FLASH_BANK0_BASE_SD
,
1183 .controller_address
= 0x400e0a00,
1184 .flash_wait_states
= 5,
1186 .size_bytes
= 1024 * 1024,
1188 .sector_size
= 8192,
1198 .base_address
= FLASH_BANK1_BASE_2048K_SD
,
1199 .controller_address
= 0x400e0c00,
1200 .flash_wait_states
= 5,
1202 .size_bytes
= 1024 * 1024,
1204 .sector_size
= 8192,
1210 /*at91sam4sd16c - LQFP100/BGA100*/
1212 .chipid_cidr
= 0x29a70ce0,
1213 .name
= "at91sam4sd16c",
1214 .total_flash_size
= 1024 * 1024,
1215 .total_sram_size
= 160 * 1024,
1226 .base_address
= FLASH_BANK0_BASE_SD
,
1227 .controller_address
= 0x400e0a00,
1228 .flash_wait_states
= 5,
1230 .size_bytes
= 512 * 1024,
1232 .sector_size
= 8192,
1242 .base_address
= FLASH_BANK1_BASE_1024K_SD
,
1243 .controller_address
= 0x400e0c00,
1244 .flash_wait_states
= 5,
1246 .size_bytes
= 512 * 1024,
1248 .sector_size
= 8192,
1254 /*at91sam4sd16b - LQFP64/BGA64*/
1256 .chipid_cidr
= 0x29970ce0,
1257 .name
= "at91sam4sd16b",
1258 .total_flash_size
= 1024 * 1024,
1259 .total_sram_size
= 160 * 1024,
1270 .base_address
= FLASH_BANK0_BASE_SD
,
1271 .controller_address
= 0x400e0a00,
1272 .flash_wait_states
= 5,
1274 .size_bytes
= 512 * 1024,
1276 .sector_size
= 8192,
1286 .base_address
= FLASH_BANK1_BASE_1024K_SD
,
1287 .controller_address
= 0x400e0c00,
1288 .flash_wait_states
= 5,
1290 .size_bytes
= 512 * 1024,
1292 .sector_size
= 8192,
1300 .chipid_cidr
= 0x247e0ae0,
1301 .name
= "atsamg53n19",
1302 .total_flash_size
= 512 * 1024,
1303 .total_sram_size
= 96 * 1024,
1314 .base_address
= FLASH_BANK_BASE_S
,
1315 .controller_address
= 0x400e0a00,
1316 .flash_wait_states
= 5,
1318 .size_bytes
= 512 * 1024,
1320 .sector_size
= 8192,
1333 /* atsamg55g19 Rev.A */
1335 .chipid_cidr
= 0x24470ae0,
1336 .name
= "atsamg55g19",
1337 .total_flash_size
= 512 * 1024,
1338 .total_sram_size
= 160 * 1024,
1349 .base_address
= FLASH_BANK_BASE_S
,
1350 .controller_address
= 0x400e0a00,
1351 .flash_wait_states
= 5,
1353 .size_bytes
= 512 * 1024,
1355 .sector_size
= 8192,
1367 /* atsamg55g19 Rev.B */
1369 .chipid_cidr
= 0x24470ae1,
1370 .name
= "atsamg55g19b",
1371 .total_flash_size
= 512 * 1024,
1372 .total_sram_size
= 160 * 1024,
1383 .base_address
= FLASH_BANK_BASE_S
,
1384 .controller_address
= 0x400e0a00,
1385 .flash_wait_states
= 5,
1387 .size_bytes
= 512 * 1024,
1389 .sector_size
= 8192,
1401 /* atsamg55j19 Rev.A */
1403 .chipid_cidr
= 0x24570ae0,
1404 .name
= "atsamg55j19",
1405 .total_flash_size
= 512 * 1024,
1406 .total_sram_size
= 160 * 1024,
1417 .base_address
= FLASH_BANK_BASE_S
,
1418 .controller_address
= 0x400e0a00,
1419 .flash_wait_states
= 5,
1421 .size_bytes
= 512 * 1024,
1423 .sector_size
= 8192,
1435 /* atsamg55j19 Rev.B */
1437 .chipid_cidr
= 0x24570ae1,
1438 .name
= "atsamg55j19b",
1439 .total_flash_size
= 512 * 1024,
1440 .total_sram_size
= 160 * 1024,
1451 .base_address
= FLASH_BANK_BASE_S
,
1452 .controller_address
= 0x400e0a00,
1453 .flash_wait_states
= 5,
1455 .size_bytes
= 512 * 1024,
1457 .sector_size
= 8192,
1477 /***********************************************************************
1478 **********************************************************************
1479 **********************************************************************
1480 **********************************************************************
1481 **********************************************************************
1482 **********************************************************************/
1483 /* *ATMEL* style code - from the SAM4 driver code */
1486 * Get the current status of the EEFC and
1487 * the value of some status bits (LOCKE, PROGE).
1488 * @param pPrivate - info about the bank
1489 * @param v - result goes here
1491 static int EFC_GetStatus(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
1494 r
= target_read_u32(pPrivate
->pChip
->target
,
1495 pPrivate
->controller_address
+ offset_EFC_FSR
,
1497 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1499 ((unsigned int)((*v
>> 2) & 1)),
1500 ((unsigned int)((*v
>> 1) & 1)),
1501 ((unsigned int)((*v
>> 0) & 1)));
1507 * Get the result of the last executed command.
1508 * @param pPrivate - info about the bank
1509 * @param v - result goes here
1511 static int EFC_GetResult(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
1515 r
= target_read_u32(pPrivate
->pChip
->target
,
1516 pPrivate
->controller_address
+ offset_EFC_FRR
,
1520 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1524 static int EFC_StartCommand(struct sam4_bank_private
*pPrivate
,
1525 unsigned command
, unsigned argument
)
1534 /* Check command & argument */
1537 case AT91C_EFC_FCMD_WP
:
1538 case AT91C_EFC_FCMD_WPL
:
1539 case AT91C_EFC_FCMD_EWP
:
1540 case AT91C_EFC_FCMD_EWPL
:
1541 /* case AT91C_EFC_FCMD_EPL: */
1542 case AT91C_EFC_FCMD_EPA
:
1543 case AT91C_EFC_FCMD_SLB
:
1544 case AT91C_EFC_FCMD_CLB
:
1545 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
1547 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1550 case AT91C_EFC_FCMD_SFB
:
1551 case AT91C_EFC_FCMD_CFB
:
1552 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1553 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1554 pPrivate
->pChip
->details
.n_gpnvms
);
1558 case AT91C_EFC_FCMD_GETD
:
1559 case AT91C_EFC_FCMD_EA
:
1560 case AT91C_EFC_FCMD_GLB
:
1561 case AT91C_EFC_FCMD_GFB
:
1562 case AT91C_EFC_FCMD_STUI
:
1563 case AT91C_EFC_FCMD_SPUI
:
1565 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1568 LOG_ERROR("Unknown command %d", command
);
1572 if (command
== AT91C_EFC_FCMD_SPUI
) {
1573 /* this is a very special situation. */
1574 /* Situation (1) - error/retry - see below */
1575 /* And we are being called recursively */
1576 /* Situation (2) - normal, finished reading unique id */
1578 /* it should be "ready" */
1579 EFC_GetStatus(pPrivate
, &v
);
1581 /* then it is ready */
1585 /* we have done this before */
1586 /* the controller is not responding. */
1587 LOG_ERROR("flash controller(%d) is not ready! Error",
1588 pPrivate
->bank_number
);
1592 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1593 pPrivate
->bank_number
);
1594 /* we do that by issuing the *STOP* command */
1595 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
1596 /* above is recursive, and further recursion is blocked by */
1597 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1603 v
= (0x5A << 24) | (argument
<< 8) | command
;
1604 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
1605 r
= target_write_u32(pPrivate
->pBank
->target
,
1606 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
1608 LOG_DEBUG("Error Write failed");
1613 * Performs the given command and wait until its completion (or an error).
1614 * @param pPrivate - info about the bank
1615 * @param command - Command to perform.
1616 * @param argument - Optional command argument.
1617 * @param status - put command status bits here
1619 static int EFC_PerformCommand(struct sam4_bank_private
*pPrivate
,
1627 int64_t ms_now
, ms_end
;
1633 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1637 ms_end
= 10000 + timeval_ms();
1640 r
= EFC_GetStatus(pPrivate
, &v
);
1643 ms_now
= timeval_ms();
1644 if (ms_now
> ms_end
) {
1646 LOG_ERROR("Command timeout");
1649 } while ((v
& 1) == 0);
1653 *status
= (v
& 0x6);
1659 * Read the unique ID.
1660 * @param pPrivate - info about the bank
1661 * The unique ID is stored in the 'pPrivate' structure.
1663 static int FLASHD_ReadUniqueID(struct sam4_bank_private
*pPrivate
)
1669 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1670 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1671 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1672 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1675 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1679 for (x
= 0; x
< 4; x
++) {
1680 r
= target_read_u32(pPrivate
->pChip
->target
,
1681 pPrivate
->pBank
->base
+ (x
* 4),
1685 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1688 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1689 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1691 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1692 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1693 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1694 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1700 * Erases the entire flash.
1701 * @param pPrivate - the info about the bank.
1703 static int FLASHD_EraseEntireBank(struct sam4_bank_private
*pPrivate
)
1706 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1710 * Erases the entire flash.
1711 * @param pPrivate - the info about the bank.
1713 static int FLASHD_ErasePages(struct sam4_bank_private
*pPrivate
,
1738 /* AT91C_EFC_FCMD_EPA
1739 * According to the datasheet FARG[15:2] defines the page from which
1740 * the erase will start.This page must be modulo 4, 8, 16 or 32
1741 * according to the number of pages to erase. FARG[1:0] defines the
1742 * number of pages to be erased. Previously (firstpage << 2) was used
1743 * to conform to this, seems it should not be shifted...
1745 return EFC_PerformCommand(pPrivate
,
1746 /* send Erase Page */
1748 (firstPage
) | erasePages
,
1753 * Gets current GPNVM state.
1754 * @param pPrivate - info about the bank.
1755 * @param gpnvm - GPNVM bit index.
1756 * @param puthere - result stored here.
1758 /* ------------------------------------------------------------------------------ */
1759 static int FLASHD_GetGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1765 if (pPrivate
->bank_number
!= 0) {
1766 LOG_ERROR("GPNVM only works with Bank0");
1770 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1771 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1772 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1776 /* Get GPNVMs status */
1777 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1778 if (r
!= ERROR_OK
) {
1779 LOG_ERROR("Failed");
1783 r
= EFC_GetResult(pPrivate
, &v
);
1786 /* Check if GPNVM is set */
1787 /* get the bit and make it a 0/1 */
1788 *puthere
= (v
>> gpnvm
) & 1;
1795 * Clears the selected GPNVM bit.
1796 * @param pPrivate info about the bank
1797 * @param gpnvm GPNVM index.
1798 * @returns 0 if successful; otherwise returns an error code.
1800 static int FLASHD_ClrGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
)
1806 if (pPrivate
->bank_number
!= 0) {
1807 LOG_ERROR("GPNVM only works with Bank0");
1811 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1812 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1813 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1817 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1818 if (r
!= ERROR_OK
) {
1819 LOG_DEBUG("Failed: %d", r
);
1822 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1823 LOG_DEBUG("End: %d", r
);
1828 * Sets the selected GPNVM bit.
1829 * @param pPrivate info about the bank
1830 * @param gpnvm GPNVM index.
1832 static int FLASHD_SetGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
)
1837 if (pPrivate
->bank_number
!= 0) {
1838 LOG_ERROR("GPNVM only works with Bank0");
1842 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1843 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1844 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
1848 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1856 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1862 * Returns a bit field (at most 64) of locked regions within a page.
1863 * @param pPrivate info about the bank
1864 * @param v where to store locked bits
1866 static int FLASHD_GetLockBits(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
1870 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1871 if (r
== ERROR_OK
) {
1872 EFC_GetResult(pPrivate
, v
);
1873 EFC_GetResult(pPrivate
, v
);
1874 EFC_GetResult(pPrivate
, v
);
1875 r
= EFC_GetResult(pPrivate
, v
);
1877 LOG_DEBUG("End: %d", r
);
1882 * Unlocks all the regions in the given address range.
1883 * @param pPrivate info about the bank
1884 * @param start_sector first sector to unlock
1885 * @param end_sector last (inclusive) to unlock
1888 static int FLASHD_Unlock(struct sam4_bank_private
*pPrivate
,
1889 unsigned start_sector
,
1890 unsigned end_sector
)
1895 uint32_t pages_per_sector
;
1897 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1899 /* Unlock all pages */
1900 while (start_sector
<= end_sector
) {
1901 pg
= start_sector
* pages_per_sector
;
1903 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1914 * @param pPrivate - info about the bank
1915 * @param start_sector - first sector to lock
1916 * @param end_sector - last sector (inclusive) to lock
1918 static int FLASHD_Lock(struct sam4_bank_private
*pPrivate
,
1919 unsigned start_sector
,
1920 unsigned end_sector
)
1924 uint32_t pages_per_sector
;
1927 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1929 /* Lock all pages */
1930 while (start_sector
<= end_sector
) {
1931 pg
= start_sector
* pages_per_sector
;
1933 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1941 /****** END SAM4 CODE ********/
1943 /* begin helpful debug code */
1944 /* print the fieldname, the field value, in dec & hex, and return field value */
1945 static uint32_t sam4_reg_fieldname(struct sam4_chip
*pChip
,
1946 const char *regname
,
1955 /* extract the field */
1957 v
= v
& ((1 << width
)-1);
1966 /* show the basics */
1967 LOG_USER_N("\t%*s: %*" PRIu32
" [0x%0*" PRIx32
"] ",
1968 REG_NAME_WIDTH
, regname
,
1974 static const char _unknown
[] = "unknown";
1975 static const char *const eproc_names
[] = {
1976 "Cortex-M7", /* 0 */
1979 "Cortex-M3", /* 3 */
1981 "arm926ejs", /* 5 */
1982 "Cortex-A5", /* 6 */
1983 "Cortex-M4", /* 7 */
1994 #define nvpsize2 nvpsize /* these two tables are identical */
1995 static const char *const nvpsize
[] = {
1998 "16K bytes", /* 2 */
1999 "32K bytes", /* 3 */
2001 "64K bytes", /* 5 */
2003 "128K bytes", /* 7 */
2004 "160K bytes", /* 8 */
2005 "256K bytes", /* 9 */
2006 "512K bytes", /* 10 */
2008 "1024K bytes", /* 12 */
2010 "2048K bytes", /* 14 */
2014 static const char *const sramsize
[] = {
2015 "48K Bytes", /* 0 */
2019 "112K Bytes", /* 4 */
2021 "80K Bytes", /* 6 */
2022 "160K Bytes", /* 7 */
2024 "16K Bytes", /* 9 */
2025 "32K Bytes", /* 10 */
2026 "64K Bytes", /* 11 */
2027 "128K Bytes", /* 12 */
2028 "256K Bytes", /* 13 */
2029 "96K Bytes", /* 14 */
2030 "512K Bytes", /* 15 */
2034 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
2035 { 0x19, "AT91SAM9xx Series" },
2036 { 0x29, "AT91SAM9XExx Series" },
2037 { 0x34, "AT91x34 Series" },
2038 { 0x37, "CAP7 Series" },
2039 { 0x39, "CAP9 Series" },
2040 { 0x3B, "CAP11 Series" },
2041 { 0x3C, "ATSAM4E" },
2042 { 0x40, "AT91x40 Series" },
2043 { 0x42, "AT91x42 Series" },
2044 { 0x43, "SAMG51 Series"
2046 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
2047 { 0x45, "SAMG55 Series (64-pin)" },
2048 { 0x47, "SAMG53 Series"
2050 { 0x55, "AT91x55 Series" },
2051 { 0x60, "AT91SAM7Axx Series" },
2052 { 0x61, "AT91SAM7AQxx Series" },
2053 { 0x63, "AT91x63 Series" },
2054 { 0x64, "SAM4CxxC (100-pin version)" },
2055 { 0x66, "SAM4CxxE (144-pin version)" },
2056 { 0x70, "AT91SAM7Sxx Series" },
2057 { 0x71, "AT91SAM7XCxx Series" },
2058 { 0x72, "AT91SAM7SExx Series" },
2059 { 0x73, "AT91SAM7Lxx Series" },
2060 { 0x75, "AT91SAM7Xxx Series" },
2061 { 0x76, "AT91SAM7SLxx Series" },
2062 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2063 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2064 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2065 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2066 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2067 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2068 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2069 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2070 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2071 { 0x92, "AT91x92 Series" },
2072 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2073 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2074 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2075 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2076 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2077 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2078 { 0xA5, "ATSAM5A" },
2079 { 0xF0, "AT75Cxx Series" },
2083 static const char *const nvptype
[] = {
2085 "romless or onchip flash", /* 1 */
2086 "embedded flash memory",/* 2 */
2087 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2088 "sram emulating flash", /* 4 */
2094 static const char *_yes_or_no(uint32_t v
)
2102 static const char *const _rc_freq
[] = {
2103 "4 MHz", "8 MHz", "12 MHz", "reserved"
2106 static void sam4_explain_ckgr_mor(struct sam4_chip
*pChip
)
2111 v
= sam4_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
2112 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
2113 v
= sam4_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
2114 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
2115 rcen
= sam4_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
2116 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
2117 v
= sam4_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
2118 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
2120 pChip
->cfg
.rc_freq
= 0;
2124 pChip
->cfg
.rc_freq
= 0;
2127 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
2130 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
2133 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
2138 v
= sam4_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
2139 LOG_USER("(startup clks, time= %f uSecs)",
2140 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
2141 v
= sam4_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
2142 LOG_USER("(mainosc source: %s)",
2143 v
? "external xtal" : "internal RC");
2145 v
= sam4_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
2146 LOG_USER("(clock failure enabled: %s)",
2150 static void sam4_explain_chipid_cidr(struct sam4_chip
*pChip
)
2156 sam4_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
2159 v
= sam4_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
2160 LOG_USER("%s", eproc_names
[v
]);
2162 v
= sam4_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
2163 LOG_USER("%s", nvpsize
[v
]);
2165 v
= sam4_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
2166 LOG_USER("%s", nvpsize2
[v
]);
2168 v
= sam4_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
2169 LOG_USER("%s", sramsize
[v
]);
2171 v
= sam4_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
2173 for (x
= 0; archnames
[x
].name
; x
++) {
2174 if (v
== archnames
[x
].value
) {
2175 cp
= archnames
[x
].name
;
2182 v
= sam4_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
2183 LOG_USER("%s", nvptype
[v
]);
2185 v
= sam4_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
2186 LOG_USER("(exists: %s)", _yes_or_no(v
));
2189 static void sam4_explain_ckgr_mcfr(struct sam4_chip
*pChip
)
2193 v
= sam4_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
2194 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2196 v
= sam4_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
2198 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
2199 pChip
->cfg
.mainosc_freq
= v
;
2201 LOG_USER("(%3.03f Mhz (%" PRIu32
".%03" PRIu32
"khz slowclk)",
2203 (uint32_t)(pChip
->cfg
.slow_freq
/ 1000),
2204 (uint32_t)(pChip
->cfg
.slow_freq
% 1000));
2207 static void sam4_explain_ckgr_plla(struct sam4_chip
*pChip
)
2209 uint32_t mula
, diva
;
2211 diva
= sam4_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2213 mula
= sam4_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2215 pChip
->cfg
.plla_freq
= 0;
2217 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2219 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2220 else if (diva
>= 1) {
2221 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
2222 LOG_USER("\tPLLA Freq: %3.03f MHz",
2223 _tomhz(pChip
->cfg
.plla_freq
));
2227 static void sam4_explain_mckr(struct sam4_chip
*pChip
)
2229 uint32_t css
, pres
, fin
= 0;
2231 const char *cp
= NULL
;
2233 css
= sam4_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2236 fin
= pChip
->cfg
.slow_freq
;
2240 fin
= pChip
->cfg
.mainosc_freq
;
2244 fin
= pChip
->cfg
.plla_freq
;
2248 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2249 fin
= 480 * 1000 * 1000;
2253 cp
= "upll (*ERROR* UPLL is disabled)";
2261 LOG_USER("%s (%3.03f Mhz)",
2264 pres
= sam4_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2265 switch (pres
& 0x07) {
2268 cp
= "selected clock";
2302 LOG_USER("(%s)", cp
);
2304 /* sam4 has a *SINGLE* clock - */
2305 /* other at91 series parts have divisors for these. */
2306 pChip
->cfg
.cpu_freq
= fin
;
2307 pChip
->cfg
.mclk_freq
= fin
;
2308 pChip
->cfg
.fclk_freq
= fin
;
2309 LOG_USER("\t\tResult CPU Freq: %3.03f",
2314 static struct sam4_chip
*target2sam4(struct target
*pTarget
)
2316 struct sam4_chip
*pChip
;
2318 if (pTarget
== NULL
)
2321 pChip
= all_sam4_chips
;
2323 if (pChip
->target
== pTarget
)
2324 break; /* return below */
2326 pChip
= pChip
->next
;
2332 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg
*pCfg
, const struct sam4_reg_list
*pList
)
2334 /* this function exists to help */
2335 /* keep funky offsetof() errors */
2336 /* and casting from causing bugs */
2338 /* By using prototypes - we can detect what would */
2339 /* be casting errors. */
2341 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
2345 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2347 NAME), # NAME, FUNC }
2348 static const struct sam4_reg_list sam4_all_regs
[] = {
2349 SAM4_ENTRY(CKGR_MOR
, sam4_explain_ckgr_mor
),
2350 SAM4_ENTRY(CKGR_MCFR
, sam4_explain_ckgr_mcfr
),
2351 SAM4_ENTRY(CKGR_PLLAR
, sam4_explain_ckgr_plla
),
2352 SAM4_ENTRY(CKGR_UCKR
, NULL
),
2353 SAM4_ENTRY(PMC_FSMR
, NULL
),
2354 SAM4_ENTRY(PMC_FSPR
, NULL
),
2355 SAM4_ENTRY(PMC_IMR
, NULL
),
2356 SAM4_ENTRY(PMC_MCKR
, sam4_explain_mckr
),
2357 SAM4_ENTRY(PMC_PCK0
, NULL
),
2358 SAM4_ENTRY(PMC_PCK1
, NULL
),
2359 SAM4_ENTRY(PMC_PCK2
, NULL
),
2360 SAM4_ENTRY(PMC_PCSR
, NULL
),
2361 SAM4_ENTRY(PMC_SCSR
, NULL
),
2362 SAM4_ENTRY(PMC_SR
, NULL
),
2363 SAM4_ENTRY(CHIPID_CIDR
, sam4_explain_chipid_cidr
),
2364 SAM4_ENTRY(CHIPID_EXID
, NULL
),
2365 /* TERMINATE THE LIST */
2370 static struct sam4_bank_private
*get_sam4_bank_private(struct flash_bank
*bank
)
2372 return bank
->driver_priv
;
2376 * Given a pointer to where it goes in the structure,
2377 * determine the register name, address from the all registers table.
2379 static const struct sam4_reg_list
*sam4_GetReg(struct sam4_chip
*pChip
, uint32_t *goes_here
)
2381 const struct sam4_reg_list
*pReg
;
2383 pReg
= &(sam4_all_regs
[0]);
2384 while (pReg
->name
) {
2385 uint32_t *pPossible
;
2387 /* calculate where this one go.. */
2388 /* it is "possibly" this register. */
2390 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2392 /* well? Is it this register */
2393 if (pPossible
== goes_here
) {
2401 /* This is *TOTAL*PANIC* - we are totally screwed. */
2402 LOG_ERROR("INVALID SAM4 REGISTER");
2406 static int sam4_ReadThisReg(struct sam4_chip
*pChip
, uint32_t *goes_here
)
2408 const struct sam4_reg_list
*pReg
;
2411 pReg
= sam4_GetReg(pChip
, goes_here
);
2415 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2416 if (r
!= ERROR_OK
) {
2417 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2418 pReg
->name
, (unsigned)(pReg
->address
), r
);
2423 static int sam4_ReadAllRegs(struct sam4_chip
*pChip
)
2426 const struct sam4_reg_list
*pReg
;
2428 pReg
= &(sam4_all_regs
[0]);
2429 while (pReg
->name
) {
2430 r
= sam4_ReadThisReg(pChip
,
2431 sam4_get_reg_ptr(&(pChip
->cfg
), pReg
));
2432 if (r
!= ERROR_OK
) {
2433 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2434 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2443 static int sam4_GetInfo(struct sam4_chip
*pChip
)
2445 const struct sam4_reg_list
*pReg
;
2449 r
= sam4_ReadAllRegs(pChip
);
2453 pReg
= &(sam4_all_regs
[0]);
2454 while (pReg
->name
) {
2455 /* display all regs */
2456 LOG_DEBUG("Start: %s", pReg
->name
);
2457 regval
= *sam4_get_reg_ptr(&(pChip
->cfg
), pReg
);
2458 LOG_USER("%*s: [0x%08" PRIx32
"] -> 0x%08" PRIx32
,
2463 if (pReg
->explain_func
)
2464 (*(pReg
->explain_func
))(pChip
);
2465 LOG_DEBUG("End: %s", pReg
->name
);
2468 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2469 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2470 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2471 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2472 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2474 LOG_USER(" UniqueId: 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08"PRIx32
,
2475 pChip
->cfg
.unique_id
[0],
2476 pChip
->cfg
.unique_id
[1],
2477 pChip
->cfg
.unique_id
[2],
2478 pChip
->cfg
.unique_id
[3]);
2483 static int sam4_protect_check(struct flash_bank
*bank
)
2486 uint32_t v
[4] = {0};
2488 struct sam4_bank_private
*pPrivate
;
2491 if (bank
->target
->state
!= TARGET_HALTED
) {
2492 LOG_ERROR("Target not halted");
2493 return ERROR_TARGET_NOT_HALTED
;
2496 pPrivate
= get_sam4_bank_private(bank
);
2498 LOG_ERROR("no private for this bank?");
2501 if (!(pPrivate
->probed
))
2502 return ERROR_FLASH_BANK_NOT_PROBED
;
2504 r
= FLASHD_GetLockBits(pPrivate
, v
);
2505 if (r
!= ERROR_OK
) {
2506 LOG_DEBUG("Failed: %d", r
);
2510 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
2511 bank
->sectors
[x
].is_protected
= (!!(v
[x
>> 5] & (1 << (x
% 32))));
2516 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command
)
2518 struct sam4_chip
*pChip
;
2520 pChip
= all_sam4_chips
;
2522 /* is this an existing chip? */
2524 if (pChip
->target
== bank
->target
)
2526 pChip
= pChip
->next
;
2530 /* this is a *NEW* chip */
2531 pChip
= calloc(1, sizeof(struct sam4_chip
));
2533 LOG_ERROR("NO RAM!");
2536 pChip
->target
= bank
->target
;
2537 /* insert at head */
2538 pChip
->next
= all_sam4_chips
;
2539 all_sam4_chips
= pChip
;
2540 pChip
->target
= bank
->target
;
2541 /* assumption is this runs at 32khz */
2542 pChip
->cfg
.slow_freq
= 32768;
2543 pChip
->probed
= false;
2546 switch (bank
->base
) {
2548 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2549 "[at91sam4s series] )",
2550 ((unsigned int)(bank
->base
)),
2551 ((unsigned int)(FLASH_BANK_BASE_S
)));
2554 /* at91sam4s series only has bank 0*/
2555 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2556 case FLASH_BANK_BASE_S
:
2557 case FLASH_BANK_BASE_C
:
2558 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2559 bank
->bank_number
= 0;
2560 pChip
->details
.bank
[0].pChip
= pChip
;
2561 pChip
->details
.bank
[0].pBank
= bank
;
2564 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2565 case FLASH_BANK1_BASE_1024K_SD
:
2566 case FLASH_BANK1_BASE_2048K_SD
:
2567 case FLASH_BANK1_BASE_C32
:
2568 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
2569 bank
->bank_number
= 1;
2570 pChip
->details
.bank
[1].pChip
= pChip
;
2571 pChip
->details
.bank
[1].pBank
= bank
;
2575 /* we initialize after probing. */
2580 * Remove all chips from the internal list without distinguishing which one
2581 * is owned by this bank. This simplification works only for one shot
2582 * deallocation like current flash_free_all_banks()
2584 static void sam4_free_driver_priv(struct flash_bank
*bank
)
2586 struct sam4_chip
*chip
= all_sam4_chips
;
2588 struct sam4_chip
*next
= chip
->next
;
2592 all_sam4_chips
= NULL
;
2595 static int sam4_GetDetails(struct sam4_bank_private
*pPrivate
)
2597 const struct sam4_chip_details
*pDetails
;
2598 struct sam4_chip
*pChip
;
2599 struct flash_bank
*saved_banks
[SAM4_MAX_FLASH_BANKS
];
2603 pDetails
= all_sam4_details
;
2604 while (pDetails
->name
) {
2605 /* Compare cidr without version bits */
2606 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
2611 if (pDetails
->name
== NULL
) {
2612 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2613 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2614 /* Help the victim, print details about the chip */
2615 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32
" decodes as follows",
2616 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2617 sam4_explain_chipid_cidr(pPrivate
->pChip
);
2620 LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32
, pDetails
->name
, pDetails
->chipid_cidr
);
2623 /* DANGER: THERE ARE DRAGONS HERE */
2625 /* get our pChip - it is going */
2626 /* to be over-written shortly */
2627 pChip
= pPrivate
->pChip
;
2629 /* Note that, in reality: */
2631 /* pPrivate = &(pChip->details.bank[0]) */
2632 /* or pPrivate = &(pChip->details.bank[1]) */
2635 /* save the "bank" pointers */
2636 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++)
2637 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
2639 /* Overwrite the "details" structure. */
2640 memcpy(&(pPrivate
->pChip
->details
),
2642 sizeof(pPrivate
->pChip
->details
));
2644 /* now fix the ghosted pointers */
2645 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
2646 pChip
->details
.bank
[x
].pChip
= pChip
;
2647 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2650 /* update the *BANK*SIZE* */
2656 static int sam4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2658 struct sam4_bank_private
*pPrivate
;
2659 int k
= bank
->size
/ 1024;
2661 pPrivate
= get_sam4_bank_private(bank
);
2662 if (pPrivate
== NULL
) {
2667 snprintf(buf
, buf_size
,
2668 "%s bank %d: %d kB at " TARGET_ADDR_FMT
,
2669 pPrivate
->pChip
->details
.name
,
2670 pPrivate
->bank_number
,
2677 static int sam4_probe(struct flash_bank
*bank
)
2680 struct sam4_bank_private
*pPrivate
;
2683 LOG_DEBUG("Begin: Bank: %u", bank
->bank_number
);
2684 if (bank
->target
->state
!= TARGET_HALTED
) {
2685 LOG_ERROR("Target not halted");
2686 return ERROR_TARGET_NOT_HALTED
;
2689 pPrivate
= get_sam4_bank_private(bank
);
2691 LOG_ERROR("Invalid/unknown bank number");
2695 r
= sam4_ReadAllRegs(pPrivate
->pChip
);
2700 if (pPrivate
->pChip
->probed
)
2701 r
= sam4_GetInfo(pPrivate
->pChip
);
2703 r
= sam4_GetDetails(pPrivate
);
2707 /* update the flash bank size */
2708 for (unsigned int x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
2709 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
2710 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
2711 LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT
" - "
2712 TARGET_ADDR_FMT
", idx %d", bank
->base
,
2713 bank
->base
+ bank
->size
, x
);
2718 if (bank
->sectors
== NULL
) {
2719 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2720 if (bank
->sectors
== NULL
) {
2721 LOG_ERROR("No memory!");
2724 bank
->num_sectors
= pPrivate
->nsectors
;
2726 for (unsigned int x
= 0; x
< bank
->num_sectors
; x
++) {
2727 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2728 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2729 /* mark as unknown */
2730 bank
->sectors
[x
].is_erased
= -1;
2731 bank
->sectors
[x
].is_protected
= -1;
2735 pPrivate
->probed
= true;
2737 r
= sam4_protect_check(bank
);
2741 LOG_DEBUG("Bank = %d, nbanks = %d",
2742 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2743 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2744 /* read unique id, */
2745 /* it appears to be associated with the *last* flash bank. */
2746 FLASHD_ReadUniqueID(pPrivate
);
2752 static int sam4_auto_probe(struct flash_bank
*bank
)
2754 struct sam4_bank_private
*pPrivate
;
2756 pPrivate
= get_sam4_bank_private(bank
);
2757 if (pPrivate
&& pPrivate
->probed
)
2760 return sam4_probe(bank
);
2763 static int sam4_erase(struct flash_bank
*bank
, unsigned int first
,
2766 struct sam4_bank_private
*pPrivate
;
2769 /*16 pages equals 8KB - Same size as a lock region*/
2774 if (bank
->target
->state
!= TARGET_HALTED
) {
2775 LOG_ERROR("Target not halted");
2776 return ERROR_TARGET_NOT_HALTED
;
2779 r
= sam4_auto_probe(bank
);
2780 if (r
!= ERROR_OK
) {
2781 LOG_DEBUG("Here,r=%d", r
);
2785 pPrivate
= get_sam4_bank_private(bank
);
2786 if (!(pPrivate
->probed
))
2787 return ERROR_FLASH_BANK_NOT_PROBED
;
2789 if ((first
== 0) && ((last
+ 1) == pPrivate
->nsectors
)) {
2792 return FLASHD_EraseEntireBank(pPrivate
);
2794 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2795 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first
, last
);
2796 for (unsigned int i
= first
; i
<= last
; i
++) {
2797 /*16 pages equals 8KB - Same size as a lock region*/
2798 r
= FLASHD_ErasePages(pPrivate
, (i
* pageCount
), pageCount
, &status
);
2799 LOG_INFO("Erasing sector: 0x%08x", i
);
2801 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
2803 if (status
& (1 << 2)) {
2804 LOG_ERROR("SAM4: Lock Region %u is locked", i
);
2807 if (status
& (1 << 1)) {
2808 LOG_ERROR("SAM4: Flash Command error @lock region %u", i
);
2816 static int sam4_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
2819 struct sam4_bank_private
*pPrivate
;
2823 if (bank
->target
->state
!= TARGET_HALTED
) {
2824 LOG_ERROR("Target not halted");
2825 return ERROR_TARGET_NOT_HALTED
;
2828 pPrivate
= get_sam4_bank_private(bank
);
2829 if (!(pPrivate
->probed
))
2830 return ERROR_FLASH_BANK_NOT_PROBED
;
2833 r
= FLASHD_Lock(pPrivate
, first
, last
);
2835 r
= FLASHD_Unlock(pPrivate
, first
, last
);
2836 LOG_DEBUG("End: r=%d", r
);
2842 static int sam4_page_read(struct sam4_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2847 adr
= pagenum
* pPrivate
->page_size
;
2848 adr
= adr
+ pPrivate
->base_address
;
2850 r
= target_read_memory(pPrivate
->pChip
->target
,
2852 4, /* THIS*MUST*BE* in 32bit values */
2853 pPrivate
->page_size
/ 4,
2856 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2857 (unsigned int)(adr
));
2861 static int sam4_set_wait(struct sam4_bank_private
*pPrivate
)
2863 uint32_t fmr
; /* EEFC Flash Mode Register */
2866 /* Get flash mode register value */
2867 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
2868 if (r
!= ERROR_OK
) {
2869 LOG_ERROR("Error Read failed: read flash mode register");
2873 /* Clear flash wait state field */
2876 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2877 fmr
|= (pPrivate
->flash_wait_states
<< 8);
2879 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
2880 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
2882 LOG_ERROR("Error Write failed: set flash mode register");
2887 static int sam4_page_write(struct sam4_bank_private
*pPrivate
, unsigned pagenum
, const uint8_t *buf
)
2893 adr
= pagenum
* pPrivate
->page_size
;
2894 adr
= (adr
+ pPrivate
->base_address
);
2896 /* 1st sector 8kBytes - page 0 - 15*/
2897 /* 2nd sector 8kBytes - page 16 - 30*/
2898 /* 3rd sector 48kBytes - page 31 - 127*/
2899 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2900 r
= target_write_memory(pPrivate
->pChip
->target
,
2902 4, /* THIS*MUST*BE* in 32bit values */
2903 pPrivate
->page_size
/ 4,
2905 if (r
!= ERROR_OK
) {
2906 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2907 (unsigned int)(adr
));
2911 r
= EFC_PerformCommand(pPrivate
,
2912 /* send Erase & Write Page */
2913 AT91C_EFC_FCMD_WP
, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2918 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2919 (unsigned int)(adr
));
2920 if (status
& (1 << 2)) {
2921 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2924 if (status
& (1 << 1)) {
2925 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2931 static int sam4_write(struct flash_bank
*bank
,
2932 const uint8_t *buffer
,
2940 unsigned page_offset
;
2941 struct sam4_bank_private
*pPrivate
;
2942 uint8_t *pagebuffer
;
2944 /* in case we bail further below, set this to null */
2947 /* ignore dumb requests */
2953 if (bank
->target
->state
!= TARGET_HALTED
) {
2954 LOG_ERROR("Target not halted");
2955 r
= ERROR_TARGET_NOT_HALTED
;
2959 pPrivate
= get_sam4_bank_private(bank
);
2960 if (!(pPrivate
->probed
)) {
2961 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2965 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2966 LOG_ERROR("Flash write error - past end of bank");
2967 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2968 (unsigned int)(offset
),
2969 (unsigned int)(count
),
2970 (unsigned int)(pPrivate
->size_bytes
));
2975 pagebuffer
= malloc(pPrivate
->page_size
);
2977 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2982 r
= sam4_set_wait(pPrivate
);
2986 /* what page do we start & end in? */
2987 page_cur
= offset
/ pPrivate
->page_size
;
2988 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2990 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2991 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2993 /* Special case: all one page */
2996 /* (1) non-aligned start */
2997 /* (2) body pages */
2998 /* (3) non-aligned end. */
3000 /* Handle special case - all one page. */
3001 if (page_cur
== page_end
) {
3002 LOG_DEBUG("Special case, all in one page");
3003 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
3007 page_offset
= (offset
& (pPrivate
->page_size
-1));
3008 memcpy(pagebuffer
+ page_offset
,
3012 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
3019 /* non-aligned start */
3020 page_offset
= offset
& (pPrivate
->page_size
- 1);
3022 LOG_DEBUG("Not-Aligned start");
3023 /* read the partial */
3024 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
3028 /* over-write with new data */
3029 n
= (pPrivate
->page_size
- page_offset
);
3030 memcpy(pagebuffer
+ page_offset
,
3034 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
3044 /* By checking that offset is correct here, we also
3045 fix a clang warning */
3046 assert(offset
% pPrivate
->page_size
== 0);
3048 /* intermediate large pages */
3049 /* also - the final *terminal* */
3050 /* if that terminal page is a full page */
3051 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3052 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
3054 while ((page_cur
< page_end
) &&
3055 (count
>= pPrivate
->page_size
)) {
3056 r
= sam4_page_write(pPrivate
, page_cur
, buffer
);
3059 count
-= pPrivate
->page_size
;
3060 buffer
+= pPrivate
->page_size
;
3064 /* terminal partial page? */
3066 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
3067 /* we have a partial page */
3068 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
3071 /* data goes at start */
3072 memcpy(pagebuffer
, buffer
, count
);
3073 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
3084 COMMAND_HANDLER(sam4_handle_info_command
)
3086 struct sam4_chip
*pChip
;
3087 pChip
= get_current_sam4(CMD
);
3094 /* bank0 must exist before we can do anything */
3095 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3099 "Please define bank %d via command: flash bank %s ... ",
3101 at91sam4_flash
.name
);
3105 /* if bank 0 is not probed, then probe it */
3106 if (!(pChip
->details
.bank
[0].probed
)) {
3107 r
= sam4_auto_probe(pChip
->details
.bank
[0].pBank
);
3111 /* above guarantees the "chip details" structure is valid */
3112 /* and thus, bank private areas are valid */
3113 /* and we have a SAM4 chip, what a concept! */
3115 /* auto-probe other banks, 0 done above */
3116 for (x
= 1; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
3117 /* skip banks not present */
3118 if (!(pChip
->details
.bank
[x
].present
))
3121 if (pChip
->details
.bank
[x
].pBank
== NULL
)
3124 if (pChip
->details
.bank
[x
].probed
)
3127 r
= sam4_auto_probe(pChip
->details
.bank
[x
].pBank
);
3132 r
= sam4_GetInfo(pChip
);
3133 if (r
!= ERROR_OK
) {
3134 LOG_DEBUG("Sam4Info, Failed %d", r
);
3141 COMMAND_HANDLER(sam4_handle_gpnvm_command
)
3145 struct sam4_chip
*pChip
;
3147 pChip
= get_current_sam4(CMD
);
3151 if (pChip
->target
->state
!= TARGET_HALTED
) {
3152 LOG_ERROR("sam4 - target not halted");
3153 return ERROR_TARGET_NOT_HALTED
;
3156 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3157 command_print(CMD
, "Bank0 must be defined first via: flash bank %s ...",
3158 at91sam4_flash
.name
);
3161 if (!pChip
->details
.bank
[0].probed
) {
3162 r
= sam4_auto_probe(pChip
->details
.bank
[0].pBank
);
3169 return ERROR_COMMAND_SYNTAX_ERROR
;
3176 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
3180 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3186 if (0 == strcmp("show", CMD_ARGV
[0])) {
3190 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
3191 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3194 command_print(CMD
, "sam4-gpnvm%u: %u", x
, v
);
3198 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3199 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3201 command_print(CMD
, "sam4-gpnvm%u: %u", who
, v
);
3204 command_print(CMD
, "sam4-gpnvm invalid GPNVM: %u", who
);
3205 return ERROR_COMMAND_SYNTAX_ERROR
;
3210 command_print(CMD
, "Missing GPNVM number");
3211 return ERROR_COMMAND_SYNTAX_ERROR
;
3214 if (0 == strcmp("set", CMD_ARGV
[0]))
3215 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3216 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3217 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
3218 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3220 command_print(CMD
, "Unknown command: %s", CMD_ARGV
[0]);
3221 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3226 COMMAND_HANDLER(sam4_handle_slowclk_command
)
3228 struct sam4_chip
*pChip
;
3230 pChip
= get_current_sam4(CMD
);
3242 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3244 /* absurd slow clock of 200Khz? */
3245 command_print(CMD
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
3246 return ERROR_COMMAND_SYNTAX_ERROR
;
3248 pChip
->cfg
.slow_freq
= v
;
3253 command_print(CMD
, "Too many parameters");
3254 return ERROR_COMMAND_SYNTAX_ERROR
;
3256 command_print(CMD
, "Slowclk freq: %d.%03dkhz",
3257 (int)(pChip
->cfg
.slow_freq
/ 1000),
3258 (int)(pChip
->cfg
.slow_freq
% 1000));
3262 static const struct command_registration at91sam4_exec_command_handlers
[] = {
3265 .handler
= sam4_handle_gpnvm_command
,
3266 .mode
= COMMAND_EXEC
,
3267 .usage
= "[('clr'|'set'|'show') bitnum]",
3268 .help
= "Without arguments, shows all bits in the gpnvm "
3269 "register. Otherwise, clears, sets, or shows one "
3270 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3274 .handler
= sam4_handle_info_command
,
3275 .mode
= COMMAND_EXEC
,
3276 .help
= "Print information about the current at91sam4 chip "
3277 "and its flash configuration.",
3282 .handler
= sam4_handle_slowclk_command
,
3283 .mode
= COMMAND_EXEC
,
3284 .usage
= "[clock_hz]",
3285 .help
= "Display or set the slowclock frequency "
3286 "(default 32768 Hz).",
3288 COMMAND_REGISTRATION_DONE
3290 static const struct command_registration at91sam4_command_handlers
[] = {
3293 .mode
= COMMAND_ANY
,
3294 .help
= "at91sam4 flash command group",
3296 .chain
= at91sam4_exec_command_handlers
,
3298 COMMAND_REGISTRATION_DONE
3301 const struct flash_driver at91sam4_flash
= {
3303 .commands
= at91sam4_command_handlers
,
3304 .flash_bank_command
= sam4_flash_bank_command
,
3305 .erase
= sam4_erase
,
3306 .protect
= sam4_protect
,
3307 .write
= sam4_write
,
3308 .read
= default_flash_read
,
3309 .probe
= sam4_probe
,
3310 .auto_probe
= sam4_auto_probe
,
3311 .erase_check
= default_flash_blank_check
,
3312 .protect_check
= sam4_protect_check
,
3314 .free_driver_priv
= sam4_free_driver_priv
,
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